6_HT-Supporting finegrained synchronization on a simultaneous multithreading pro.pdf - Proceedings of the 5th International Symposium on High

6_HT-Supporting finegrained synchronization on a simultaneous multithreading pro.pdf

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Proceedings of the 5th International Symposium on High Performance Computer Architecture, January 1999. Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor Dean M. Tullsen Dept. of Computer Science and Engineering University of California, San Diego [email protected] Jack L. Lo Transmeta Corporation Santa Clara, CA [email protected] Susan J. Eggers, Henry M. Levy Dept. of Computer Science and Engineering University of Washington eggers,levy @cs.washington.edu Abstract This paper proposes and evaluates new synchronization schemes for a simultaneous multithreaded processor. We present a scalable mechanism that permits threads to cheaply synchronize within the processor, with blocked threads con- suming no processor resources. We also introduce the concept of lock release prediction, which gains an additional improve- ment of 40%. Overall, we show that these improvements in synchronization cost enable parallelization of code that could not be effectively parallelized using traditional techniques. 1. Introduction The performance of a multiprocessor’s synchronization mechanisms determine the granularity of parallelism that can be exploited on that machine. Synchronization on a conven- tional multiprocessor carries a high cost due to the hardware levels at which synchronization and communication must oc- cur (e.g., main memory). As a result, compilers and program- mers must decompose parallel applications in a coarse-grained way in order to reduce synchronization overhead. This paper examines fine-grained synchronization on a si- multaneous multithreaded (SMT) processor — a processor in which the CPU can issue instructions from multiple threads in a single cycle [10, 9]. Multithreaded processors provide an opportunity to greatly decrease synchronization cost, because the communicating threads are internal to a single processor. While previous work has shown the benefits of SMT on par- allel workloads [6, 7], those studies relied on traditional syn- chronization mechanisms, ignoring the potential advantages (and problems) of synchronizing in an SMT CPU. A simultaneous multithreading processor differs from a conventional multiprocessor in several crucial ways that in- fluence the design of SMT synchronization: (1) Threads on an SMT processor compete for all fetch and execution re- sources each cycle. Synchronization mechanisms (e.g., spin locks) that consume any shared resources without making progress, can impede other threads. (2) Data shared by threads is held closer to the processor, i.e., in the thread-shared L1 cache; therefore, communication is dramatically faster be- tween threads. Synchronization must experience a similar in- crease in performance to avoid becoming a bottleneck. (3) Hardware thread contexts on an SMT processor share func- tional units. This opens the possibility of communicating syn- chronization and/or data much more effectively than through memory.
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