fa99 midterm2

# Computer Organization and Design: The Hardware/Software Interface

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CS152 Fall ’99 Midterm II Page 1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm II November 17, 1999 CS152 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score 1 25 2 25 3 25 4 25 Total

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CS152 Fall ’99 Midterm II Page 3 Problem 1: Memory Hierarchy Problem 1a: Assume that we have a 32-bit processor (with 32-bit words) and that this processor is byte-addressed (i.e. addresses specify bytes). Suppose that it has a 512-byte cache that is two- way set-associative, has 4-word cache lines, and uses LRU replacement. Split the 32-bit address into “tag”, “index”, and “cache-line offset” pieces. Which address bits comprise each piece? tag: index: cache-line offset: Problem 1b: How many sets does this cache have? Explain. Problem 1c: Draw a block diagram for this cache. Show a 32-bit address coming into the diagram and a 32-bit data result and “Hit” signal coming out. Include, all of the comparators in the system and any muxes as well. Include the data storage memories (indexed by the “Index”), the tag matching logic, and any muxes. You can indicate RAM with a simple block, but make sure to label address widths and data widths. Make sure to label the function of various blocks and the width of any buses.

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CS152 Fall ’99 Midterm II Page 5 Problem 1d: Below is a series of memory read references set to the cache from part (a). Assume that the cache is initially empty and classify each memory references as a hit or a miss. Identify each miss as either compulsory, conflict, or capacity. One example is shown. Hint: start by splitting the address into components. Show your work. Address Hit/Miss? Miss Type? 0x300 Miss Compulsory 0x1BC 0x206 0x109 0x308 0x1A1 0x1B1 0x2AE 0x3B2 0x10C 0x205 0x301 0x3AE 0x1A8 0x3A1 0x1BA Problem 1e: Calculate the miss rate and hit rate.

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CS152 Fall ’99 Midterm II Page 7 Problem 1f: You have a 500 MHz processor with 2-levels of cache, 1 level of DRAM, and a DISK for virtual memory. Assume that it has a Harvard architecture (separate instruction and data cache at level 1). Assume that the memory system has the following parameters: Component Hit Time Miss Rate Block Size First-Level Cache 1 cycle 4% Data 1% Instructions 64 bytes Second-Level Cache 20 cycles + 1 cycle/64bits 2% 128 bytes DRAM 100ns+ 25ns/8 bytes 1% 16K bytes DISK 50ms + 20ns/byte 0% 16K bytes Finally, assume that there is a TLB that misses 0.1% of the time on data (doesn’t miss on

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