Computer Organization and Design: The Hardware/Software Interface

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I October 6, 1999 CS152 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score 12 0 21 5 33 5 43 0 Total
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2 Problem 1: Performance Problem 1a: Name the three principle components of runtime that we discussed in class. How do they combine to yield runtime? Problem 1b: What is Amdahl’s law for speedup? State as a formula which includes a factor for clock rate. Let us suppose that you have been running an important program on your company’s 300MHz Acme II processor. By running a detailed simulator, you were able to collect the following instruction mix and breakdown of costs for ezach instruction type: Instruction Class Frequency (%) Cycles Integer arithmetic and logical 40 1 Load 20 1 Store 10 2 Branches 20 3 Floating Point 10 5 Problem 1c : What is the CPI and MIPS rating of the Acme II for this program? Problem 1d: Suppose that you turn on the optimizer and it eliminates 30% of the arithmetic/logic instructions (i.e. 12% of the total instructions), 30% of load instructions, and 20% of the floating-point instructions. None of the other instructions are effected. What is the speedup of the optimized program? (Be sure to state the formula that you are using for speedup and show your work)
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3 Problem 1e: What is the CPI and MIPS rating with the optimized version of the program? Compare your result to that of (1c) and explain the difference: Problem 1f: Now, suppose that the Acme III has just been introduced with a faster clock rate (450 MHz). However, in order to make the clock rate faster, the Acme engineers had to increase the CPI for arithmetic, logical, and load instructions to 2 cycles and floating point instructions to 6 cycles. What is the speedup of the Acme III over the Acme II on the unoptimized program? Show work Problem 1g: The engineers for Acme Inc are currently working on the Acme IV. Instead of increasing the clock rate again, they are working on reducing the time for the floating-point instructions. Use Amdahl’s law to show the maximum speedup that you could expect between the Acme III and Acme IV on the u noptimized program (if the clock rates are both 450 MHz)?
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4 Problem 2: Propagation Delay Problem 2a: Assume the following characteristics for NAND gates: Input load: 150fF, Internal delay: TPlh=0.2ns, TPhl=0.5ns, Load-Dependent delay: TPlhf=.0020ns, TPhlf=.0021ns For the circuit below, assume that inputs X 0 – X 5 are all set to 1. What are the propagation delays from A to Y (for rising and falling-edges of Y)? X 0 A X 1 Y Z X 2 X 3 X 4 X 5
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5 Problem 2b : Suppose that we construct a new gate, XOR, as follows: Compute the standard parameters for the linear delay models for this complex gate, assuming the parameters given above for the NAND gate: A Input Capacitance: Load-dependent Delays: B Input Capacitance: TPAYlhf: TPAYhlf: TPBYlhf: TPBYhlf: Internal delays for A Y, assuming that B is set to 1 (worst case delays): TPAYlh: TPAYhl: Problem 2c: Now, suppose we use our new XOR gate in the circuit below.
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fa99 midterm1 - University of California, Berkeley College...

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