fa01 midterm1

# Computer Organization and Design: The Hardware/Software Interface

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2001 John Kubiatowicz Midterm I March 1, 2001 CS152 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score 1 20 2 20 3 30 4 30 Total

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3 Problem 1: Performance Problem 1a : Name the three principle components of runtime that we discussed in class. How do they combine to yield runtime? Now, you have analyzed a benchmark that runs on your company’s processor. This processor runs at 300MHz and has the following characteristics: Instruction Type Frequency (%) Cycles Arithmetic and logical 35 1 Load and Store 25 2 Branches 25 3 Floating Point 15 5 Your company is considering a cheaper, lower-performance version of the processor. Their plan is to remove some of the floating-point hardware to reduce the die size. The wafer on which the chip is produced has a diameter of 10cm, a cost of \$2000, and a defect rate of 1 / (cm 2 ). The manufacturing process has an 80% wafer yield and a value of 2 for α . Here are some equations that you may find useful: The current procesor has a die size of 12mm × 12mm. The new chip has a die size of 10mm × 10mm, and floating point instructions will take 13 cycles to execute. Problem 1b : What is the CPI and MIPS rating of the original processor? ± ² area die 2 diameter wafer area die diameter/2 wafer dies/wafer u u S ³ u S 2 D ³ ¸ ¹ · ¨ © § D u ´ u area die area unit per defects 1 yield wafer yield die

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4 Problem 1c: What is the CPI and MIPS rating of the new processor? Problem 1d: What is the original cost per (working) processor? Problem 1e: What is the new cost per (working) processor? Problem 1f: Assume that we are considering the other direction of improving the original processor by increasing the speed of floating point. What is the best possible speedup that we could get, and what would the CPI and MIPS rating be of the new processor?
5 Problem 2: Parallel Prefix Assume the following characteristics for NAND gates: Input load: 120fF, Internal delay: TPlh=0.3ns, TPhl=0.6ns, Load-Dependent delay: TPlhf=.0020ns, TPhlf=.0021ns Problem 2a: Suppose that we construct an XOR, as follows: Compute the standard parameters for the linear delay models for this complex gate, assuming the parameters given above for the NAND gate. Assume that a wire doubles the input capacitance of the gate that it is attached to: A Input Capacitance: Load-dependent Delays: B Input Capacitance : TPAYlhf: TPAYhlf: TPBYlhf: TPBYhlf: Maximum Internal delays for A Y: TPAYlh: TPAYhl: A B Y

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6 An important operation that shows up in many different contexts is the parallel prefix circuit using XOR as the combining operation. This circuit takes as input a sequence of bits, such as: [ I 0 , I 1 , I 2 , I 3 , ] then outputs a new sequence, [O 0 , O 1 , O 2 , O 3 ,…] which is the same length. The output bits are related to the input bits in the following fashion: [ O 0 =I 0 , O 1 =(I 0 I 1 ), O 2 =(I 0 I 1 I 2 ), O 3 =(I 0 I 1 I 2 I 3 ), …] Each successive output bit is the XOR of the new input bit and the previous output bit.
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