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Unformatted text preview: 64 bytes Second-Level Cache 20 cycles + 1 cycle/64bits 2% 128 bytes DRAM 100ns+ 25ns/8 bytes 1% 16K bytes TLB 1 cycle 0.1% 16K bytes Finally, assume that the TLB has a fill penalty of 40 cycles. Question 1: Assume that the DRAM miss rate refers to a page fault. The DISK parameters are: Drive rotates at 12000RPM, transfer rate 32 MB/second, 10ms average seek time. What is the “Miss Penalty” for filling a DRAM page? You can treat MB=10 6 bytes and KB=10 3 bytes. Question 2: Write an equation for AMAT data as seen by the processor. You do not have to generate an actual number. This equation should evaluate to a time in “ns”, so make sure to check units. Hint: using a set of equations with symbolic values is probably the simplest thing to do....
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- Spring '04
- Computer Architecture, Central processing unit, CPU cache, Harvard Architecture, Berkeley College of Engineering Computer Science, Cache DRAM TLB