Embedded Memory.pdf - Memory Project CECS 460 CSULB Description • Since this project is a means to demonstrate proficiency in Verilog design and

Embedded Memory.pdf - Memory Project CECS 460 CSULB...

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Memory Project CECS 460 CSULB
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Description Since this project is a means to demonstrate proficiency in Verilog design and utilization of the TramelBlaze the details of the implementation will be left to the designer - previous projects have had their detailed design presented by the instructor This project will involve the inclusion of a Xilinx memory within the FPGA
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Overall Picture The memory should be a 32K x 16 SRAM - this will require 1/2 of the memory space of the TramelBlaze The timing of the TramelBlaze has been demonstrated to interface correctly with the memory The address decoder will need to be
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Unformatted text preview: modified and the data routing back to the TramelBlaze will have to be modified FPGA TramelBlaze UART 32K x 16 SRAM Software Description • In the initialization portion of the code there should be a test of the memory performed • AAAAs, 5555s, Address, Address bar • In operation every byte received from the UART should be stored in the SRAM - never clear data • Every time a “%” is received the TramelBlaze should dump the contents of the memory to the terminal Due • Due last day of class • Chip spec due the day of the final...
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