AddressDecoding.pdf - Address Decoding CSULB CECS 460 Typical Processor Architecture Address and Data Address bus Data bus RAM is typically used for

AddressDecoding.pdf - Address Decoding CSULB CECS 460...

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Address Decoding CSULB CECS 460
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Typical Processor Architecture Address and Data Each processor architecture will have the number of address bits (M) and the number of data bits (N) defined N defines how many bits are transferred on each transaction M defines how many possible address may be referenced — 2^M RAM is typically used for data storage ROM is typically used for instructions and constants I/O enables to processor to communicate with system interfaces Address bus Data bus
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Problem When writing the software to run in the processor there must be a way to uniquely identify all of the resources available to the processor: RAM, ROM & I/O The source and destination of all bus transactions are the processor registers The processor address bus is the “pointer” for all bus transactions (READs/WRITEs) READ: REGISTER <— M[Address] Write: M[Address] <— REGISTER The information is referenced by the ADDRESS BUS The information is exchanged by the DATA BUS
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Example: Apple II (A simple Architecture)
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