Full UART S19.pdf - Full UART Transmitter Receiver CSULB CECS 460 Spring 2019 Full UART • In both class lectures and posted videos the full UART has

Full UART S19.pdf - Full UART Transmitter Receiver CSULB...

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Full UART Transmitter & Receiver CSULB CECS 460 Spring 2019
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Full UART In both class lectures and posted videos the full UART has been presented In this project you will create the full UART as an IP in your design Your transmit will be instantiated in the UART and the connections will be adjusted The block diagram will document what your design should include at this point The following diagrams review the transmit, cover the receive from both the data path and control perspective, and show the top level design
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Address Decoder The TramelBlaze needs to access data from a variety of sources within the SOC To generate specific enables the design requires an address decoder to generate the write and read enables This design generates 8 write enables and 8 read enables If your design requires more enables just add more PORT_ID bits
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Transmit Review
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UART Top Level
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UART Top Level UART top level will have the TX engine and the RX engine along with supplemental logic Configuration bits (switches) should be read in the initialization code and be stored in a register in the UART. This register should be the source of the configuration to the UART Baud rate decoder should generate k and k/2 Multiplexer selects between the switches, the UART data and the UART status The tx_rdy and rx_rdy signals need to be run through PED circuits in order to generate the interrupt to the TramelBlaze
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Receive Engine Control
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Receive Engine Control The goal of the receive engine is to synchronize the data collection
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