ADL Assignment - Assignment 1 8 bit counter.3 A Verilog Version.3 a Verilog behavior module for 8 bit counter.3 b Verilog testbench for 8 bit

ADL Assignment - Assignment 1 8 bit counter.3 A...

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Assignment 1 8 bit counter ..................................................................................................................................... 3 A. Verilog Version ............................................................................................................................ 3 a) Verilog behavior module for 8 bit counter ........................................................................... 3 b) Verilog testbench for 8 bit counter ....................................................................................... 3 c) Verilog simulation results for 8 bit counter ......................................................................... 4 B. VHDL Version .............................................................................................................................. 5 a) VHDL behavior module for 8 bit counter ............................................................................. 5 b) VHDL testbench for 8 bit counter ......................................................................................... 5
c) VHDL simulation results for 8 bit counter ........................................................................... 7 D-type flip-flop and its’divide ......................................................................................................... 7 A. A positive triggered D-type flip-flop .......................................................................................... 7 12
8 bit counter A. Verilog Version a) Verilog behavior module for 8 bit counter `timescale 1ns / 1ps //behavioral 8 bit counter unit module count8 (clk, reset, out); //define inputs and outputs input reset, clk; output [7:0] out; //declare outputs as reg reg [7:0] out; //at the time of clk posedge, when reset=1, out=0, otherwise out++ always @ (posedge clk) begin if (reset) out = 8'b0000_0000; else out = out + 8'b0000_0001; end endmodule b) Verilog testbench for 8 bit counter `timescale 1ns / 1ps module count8_tb; reg reset, clk; wire [7:0] out; parameter clk_period = 30; //display variables initial $monitor ("Time = %t, reset = %b, count = %d(%b)", $time, reset, out, out); //apply input initial
clk = 0; always #(clk_period/2) clk <= ~clk; initial begin #80 reset = 1'b0; #25 reset = 1'b1; #15 reset = 1'b0; #100 reset = 1'b1; #10 reset = 1'b0; #500 reset = 1'b1; #10 reset = 1'b0; #29 reset = 1'b1; #6 reset = 1'b0; #18 reset = 1'b1; #3000 $stop; end //instantiate the module count8 instl ( .reset(reset), .clk(clk), .out(out) ); endmodule c) Verilog simulation results for 8 bit counter The results of synopsys shown as following The results of ISIM simulator shown as following
B. VHDL Version a) VHDL behavior module for 8 bit counter //behavioral 8 bit counter unit library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; //define entity entity count8 is port (clk, reset : in std_logic; count : out std_logic_vector(7 downto 0)); end count8; //define architecture architecture behavior of count8 is signal count1 : std_logic_vector(7 downto 0); begin process (clk, reset) begin if (reset = '1') then count1 <= (others => '0'); elsif (clk'event and clk = '1') then count1 <= count1 + 1; end if; end process; count <= count1; end behavior; b) VHDL testbench for 8 bit counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;
c) VHDL simulation results for 8 bit counter The results of synopsys shown as following The results of ISIM simulator shown as following

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