hw1.docx - 1 module testAll_tb parameter n=8 reg clk...

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1. module testAll_tb; parameter n=8; reg clk; reg[n-1:0] count; wire f; testAll u1(f, count); initial begin clk=1; count=0; end always #1 clk=~clk; always @(posedge clk) count=count+1; endmodule library ieee; use ieee.std_logic_1164.all; entity testALL _tb is end entity testAll_tb; architecture trans of testAll_tb is component testAll port( clk :in std_logic; f :out std_logic; ); end component; signal clk : std_logic; signal rst : std_logic; signal count : std_logic_vector(n-1 downto 0); signal f: std_logic; begin instantiation:testAll port map ( rst=>rst, clk=>clk, );
clk_gen:process begin wait for 50ns; clk<='1'; count<=count+"1"; wait for 5000ns; end process; end trans; 2. module counter8(clk,rst,out); output[7:0] out; input clk,rst; reg[7:0] out; [email protected](posedge clk) begin if(rst) out<=8'b0; else if(out==8'b11111111) out<=8'b0; else out<=out+1; end endmodule module counter8_tb; reg clk, rst; wire[7:0]out; counter8 u1(.clk(clk),.rst(rst),.out(out)); initial begin rst=1; clk=1; #5 rst=0; end always #1 clk=~clk; endmodule
Verilog waveform library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity count8 is port ( rst : in std_logic; clk : in std_logic; outl : out std_logic_vector(7 downto 0) ); end entity count8; architecture trans of count8 is signal out0 : std_logic_vector(7 downto 0); begin outl <= out0; process (clk,rst) begin if (rst = '1') then out0 <= "00000000"; elsif rising_edge(clk) then out0 <= out0 + "00000001"; end if; end process; outl <= out0; end architecture trans;
library ieee; use ieee.std_logic_1164.all; entity test_count8 is

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