spr97 midterm1 solution

# Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Computer Science Division Department of Electrical Engineering and Computer Sciences University of California, Berkeley Sp97 D.K. Jeong Midterm #1 March 3, 1997 Name Key SID Number Discussion Section You may bring one double-sided note. You have 180 minutes. Please write your name on this cover and also at the top left of each page. The point value of each question is indicated in brackets after it. Make sure to show your work to get at least partial credit. Problem Possible Score 1 15 2 20 3 10 4 20 5 15 Total 80

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Name: Question 1. (Performance) [15 pts] You are to improve cost/performance on an existing system based on a single-chip microprocessor having the following parameters. Base Machine Clock Frequency 100MHz Die Size 10 mm x 10 mm Instruction Mix int 62 % FP 38 % CPI int 1.6 FP 4.2 (a) What is the MIPS number of the base machine? [2 pts] CPI = Σ CPI i * IC I , where CPI is cycles per instruction, and IC is instruction count. CPI = 1.6*.62 + 4.2 * .38 = 2.588 MIPS = Clk freq/CPI = 100 MHz/2.588 = 38.64 MIPS By using an optimizing compiler, the number of FP instructions is reduced by 20% and int instructions by 10% for the same application program. (b) What is the new MIPS number of the base machine when using the optimizing compiler? (Instruction mix is changed!)[2 pts] Instruction mix has changed, so that there is a different proportion of FP and int instructions. Therefore, we need to recalculate CPI: CPI = (0.9 *.62*1.6 + .8*.38*4.2) / (.9*.62 + .8*.38) = 2.5169 The denominator represents the decrease in Instruction Count, due to the optimizing compiler. MIPS_comp = Clk freq/CPI = 100MHz/2.5169 = 39.73 MIPS
(c) When running the same application, how much performance gain do you expect from using such an optimizing compiler? [2 pts] MIPS is about the same, but IC has reduced. The relative performance is given by: Performance_comp = . 38.64 MIPS . = 1.128 Performance_base 39.73 MIPS / (.9*.62 + .8*.38) The optimizing compiler improves performance by 12.8%. By re-designing an FP hardware, die size will be increased by 20%, its FP CPI will be reduced to 2.8, clock frequency will remain as the same. (d) What is the new MIPS number of this improved machine with an ordinary compiler? [2 pts] CPI = 1.6*.62 + .38*2.8 = 2.056 MIPS = 100 MHz/2.056 = 48.64 MIPS (e) Assuming die yield is proportional to the inverse of the cube of the die size, how much additional cost do you expect? Assume that the number of dies per wafer is inversely proportional to the die size and that all the cost is proportional to the die.[2 pts] Cost is inversely proportional to yield—as yield goes down, cost goes up. The yield goes down by the cube of the area: if the area goes up by 1.2x, the yield goes down by (1.2) 3 x . Also, we can fit less dies on a wafer as the area goes up. If the area increases by 1.2x, we can fit 1.2x less dies per wafer. Since the cost per wafer stays the same, the cost per die goes up.

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• Spring '04
• Kubiatowicz
• Computer Architecture, Trigraph, Clock rate, Central processing unit, MIPS architecture, Sticky bit

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