Prof. Robert C. Leachman
IEOR 130, Methods of Manufacturing Improvement
Yield losses from wafer fabrication take two forms:
. Line yield
losses result from physical damage of the wafers due to mishandling, or by mis-
processing of the wafer (e.g., skipping or duplicating a process step, wrong recipe,
equipment out of control, etc.). Mis-processing is detected either by in-line inspections
interspersed through the wafer fabrication process or by an electrical parametric test of a
special test pattern on the wafer. This parametric test is almost always performed just
before the wafer leaves the fabrication facility to go to the wafer probe area. It is also
sometimes performed at one or more points within the wafer fabrication process flow.
Many die yield losses are the result of tiny
Defects are defined as any physical
anomaly that causes a circuit to fail. This includes shorts or resistive paths or opens
caused by particles, excess metal that bridges across steep underlying contours causing
shorts, photoresist splatters and flakes, weak spots in insulators, pinholes, opens due to
step coverage problems, scratches, etc.
It is natural to think of defects as being randomly distributed across the wafer surface,
and to speak about the
of defects on the wafer surface, i.e., the number of circuit
faults per unit area. If we postulate that a die will not work unless it is completely free of
defects, then the probability that a die works is the probability that no defects lie within
its area. Obviously, the larger the die area, the more the chance it includes one or more
defects, and so the less the probability that the die works. Thus wafers with large die
printed on them will have a lower die yield than will wafers with small die printed on
them, if the two types of wafers are made in the same fabrication process and are subject
to the same density of defects.
To fairly compare die yields of products with different die areas made in different
factories, it is desirable to find the underlying defect density in each factory. A factory
with a lower defect density is capable of producing with a higher die yield.
Not all die yield losses are due to defects. Some mis-processing escapes detection at in-
line optical inspections in the fabrication process as well as at parametric test. A
prevalent example is
. The thickness of films deposited on the wafer is often
well-controlled across the central portion of the wafer but poorly controlled near the edge
of the wafer, resulting in wholesale die yield losses near the edge. Parametric test and in-
line inspections typically are performed on a sample basis and exclude edge die. Hence
edge losses show up as die yield loss, even though they are not the result of defects.