Lec07Sys - 68HC12 Features 16-bit CPU12 Upwardly compatible...

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ECE 471 7-Sys-1 Lecture 7. Systems Configuration Outline Reset State Mode of operation Resource Mapping Resource Precedence System Configuration “C” Startup Code
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ECE 471 7-Sys-2 68HC12 Features 16-bit CPU12: Upwardly compatible with the M68HC11 instruction set – Interrupt stacking and programmer’s model identical to the M68HC11 – 20-bit arithmetic logic unit (ALU) [for accuracy] – Instruction queue [pipelined] – Enhanced indexed addressing [convenient to use] – Fuzzy logic instructions [convenient to use] Multiplexed bus – Single chip or expanded Memory – 32-Kbyte FLASH, 32-Kbyte ROM (some members), 768-byte EEPROM, 1-Kbyte random-access memory (RAM) with single-cycle access 8-channel, 10-bit analog-to-digital converter (ATD) 8-channel standard timer module (TIM) — some members Enhanced capture timer (ECT) — MC68HC12BE32 only
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ECE 471 7-Sys-3 68HC12 Features 16-bit pulse accumulator for event counting and time accumulation Pulse-width modulator (PWM) - 8-bit, 4-channel or 16-bit, 2- channel Serial interfaces - Asynchronous and Synchronous serial peripheral interface (SCI & SPI) J1850 data link communication (BDLC), MC68HC912B32 and MC68HC12BE32 only Controller area network (CAN), MC68HC(9)12BC32 only Computer operating properly (COP) watchdog timer, clock monitor, and real-time interrupt timer Slow-mode clock divider Up to 63 general-purpose input/output (I/O) lines Single-wire background debug mode (BDM) On-chip hardware breakpoints
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ECE 471 7-Sys-4 Member of 68HC12 Family
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ECE 471 7-Sys-5
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ECE 471 7-Sys-6
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ECE 471 7-Sys-7 Microcontroller Configuration Microcontroller is is designed for general use can be used in one of many different configurations needs to be configured in system level (hardware and software) in component level (hardware and
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