Lec09Int

Lec09Int - Interrupts Get immediate attention of the processor Code executed in response to an interrupt is an Interrupt Service Routine Interrupts

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EE471 9-Int-1 Lecture 9. Reset and Interrupts Outline Maskable and non-maskabke interrupt Interrupt priority Interrupt vector table Edged triggered and level triggered interrupt Types of reset Configure watch dog timer Configure real-time interrupt
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EE471 9-Int-2 Interrupts Get immediate attention of the processor. Code executed in response to an interrupt is an Interrupt Service Routine. Interrupts are used by many peripheral functions. Approximately 25 interrupt sources depending on the processor type. A return address is pushed on the stack to allow a return to the main program after the interrupt service routine.
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EE471 9-Int-3 Reset and Interrupts are Exceptions Each exception has a 16-bit vector that points to the starting address of the associated exception-handling routine. Vectors are stored in the upper 128 bytes of the standard 64-Kbyte address map. The six highest vector addresses are used for resets and non-maskable interrupt sources. The remainder of the vectors are used for maskable interrupts. All vectors must be initialized.
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EE471 9-Int-4 Nonmaskable Interrupt Nonmaskable interrupts include 1. Power-on reset (POR) or RESET pin 2. Clock monitor reset 3. Computer operating properly watchdog reset 4. Unimplemented instruction trap 5. Software interrupt instruction (SWI) 6. XIRQ signal if X bit in CCR = 0
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EE471 9-Int-5 Maskable interrupt Maskable interrupt sources include Many on-chip peripheral systems External interrupt service requests. Maskable Interrupts are recognized when the global interrupt mask bit (I) in the condition code register (CCR) is cleared. The default state of the I bit out of reset is 1 I bit of CCR can be written at any time.
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EE471 9-Int-6 Exception Priority When multiple interrupts arrives at the same time, the priorities of the sources are shown as following table. Interrupt sources are prioritized by default Any one maskable interrupt source may be assigned the highest priority among maskable interrupts by means of the HPRIO register. The relative priorities of the other sources remain the same.
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EE471 9-Int-7 Edge or Level Trigged Interrupts IRQ can be selected as an edge trigged or level-triggered interrupt. If IRQ is selected as an edge-triggered interrupt. As long as the
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This note was uploaded on 01/31/2008 for the course ECE 471 taught by Professor Chien during the Spring '08 term at IUPUI.

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Lec09Int - Interrupts Get immediate attention of the processor Code executed in response to an interrupt is an Interrupt Service Routine Interrupts

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