{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Lec09Int - Interrupts Get immediate attention of the...

Info icon This preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
EE471 9-Int-1 Lecture 9. Reset and Interrupts Outline Maskable and non-maskabke interrupt Interrupt priority Interrupt vector table Edged triggered and level triggered interrupt Types of reset Configure watch dog timer Configure real-time interrupt
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
EE471 9-Int-2 Interrupts Get immediate attention of the processor. Code executed in response to an interrupt is an Interrupt Service Routine. Interrupts are used by many peripheral functions. Approximately 25 interrupt sources depending on the processor type. A return address is pushed on the stack to allow a return to the main program after the interrupt service routine.
Image of page 2
EE471 9-Int-3 Reset and Interrupts are Exceptions Each exception has a 16-bit vector that points to the starting address of the associated exception-handling routine. Vectors are stored in the upper 128 bytes of the standard 64-Kbyte address map. The six highest vector addresses are used for resets and non-maskable interrupt sources. The remainder of the vectors are used for maskable interrupts. All vectors must be initialized.
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
EE471 9-Int-4 Nonmaskable Interrupt Nonmaskable interrupts include 1. Power-on reset (POR) or RESET pin 2. Clock monitor reset 3. Computer operating properly watchdog reset 4. Unimplemented instruction trap 5. Software interrupt instruction (SWI) 6. XIRQ signal if X bit in CCR = 0
Image of page 4
EE471 9-Int-5 Maskable interrupt Maskable interrupt sources include Many on-chip peripheral systems External interrupt service requests. Maskable Interrupts are recognized when the global interrupt mask bit (I) in the condition code register (CCR) is cleared. The default state of the I bit out of reset is 1 I bit of CCR can be written at any time.
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
EE471 9-Int-6 Exception Priority When multiple interrupts arrives at the same time, the priorities of the sources are shown as following table. Interrupt sources are prioritized by default Any one maskable interrupt source may be assigned the highest priority among maskable interrupts by means of the HPRIO register. The relative priorities of the other sources remain the same.
Image of page 6
EE471 9-Int-7 Edge or Level Trigged Interrupts IRQ can be selected as an edge trigged or level-triggered interrupt.
Image of page 7

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern