6301-7.pdf - EE\/CE 6301 Advanced Digital Logic Bill Swartz Dept of EE Univ of Texas at Dallas EEDG\/CE6301 \u2013 B Swartz 1 Session 07 Multi-Level

6301-7.pdf - EE/CE 6301 Advanced Digital Logic Bill Swartz...

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1EE/CE 6301: Advanced Digital LogicBill SwartzDept. of EEUniv. of Texas at DallasEEDG/CE6301 B. Swartz
2Multi-Level OptimizationSession 07Adapted from the work of M Nourani to whom I am grateful
3Motivation for Multi-Level Optimization
4General FormGeneral circuits may haveSums within productsProducts within sumsArbitrary depthExample: z=((a.(b+c)+e).f.g+h).i
5Example Two-Level vs. Multi-LevelConsider the minimal 2-level SOP form# AND3 = 6; # OR7 = 1 Total = 7 gates# gate inputs = 25This can be improved if we replace the 2-level form with a multi-level, factored form# AND3 = 1; # OR2 = 2; # OR3 = 1 Total = 4 gates!# gate inputs = 10deyZfgabcxfydexabcgZadfaefbdfbefcdfcefgZadaebdbecdcefgZabc dabc efgZabcdefg
6Consideration of CostTwo-level implementation for most practical circuits will be too expensive.Example: 16-bit adder (32 bits inputs, huge number 216to 232product terms)Two-level is natural for Programmable Logic Array (PLA). Inefficient, hence folded PLAs.Many of datapath logic are designed by integrating/interfacing modules. A multi-level architecture will be created.
7Multi-Level Optimization Methods
8Fundamental TechniquesCubesTransformationsFactorizationDecompositionExtractionSubstitutionCollapsingShannon ExpansionDivisionWeak (Algebraic)Strong (Boolean)
Boolean Cubes9We can represent the truth table of an n-input Boolean function a n-dimensional cubeEach axis represent one variable or literal and can be either 0 or 1Some example cubes
10Boolean CubesCubes are denoted by their literalsor the positive logic variablesExamplesaabxyzwxyz
11Transformations
12Factorization Example 1Multi-level logic can be less expensiveOriginal form7 gates: 6 AND4, 1 OR6After factorization:3 gates: 1 OR2, 1 OR3, 1 AND4))((gfedcabzabegabdgabcgabefabdfabcfz
13Factorization Example 2Multi-level logic can be less expensiveOriginal form5 gates: 4 AND2, 1 OR5, 9 literalsAfter factorization:4 gates: 3 OR2, 1 AND2, 5 literalsedcbaz))((ebdbcadacz
14Decomposition Example 1Original form5 gates: 4 AND3, 1 OR4After decomposition:5 gates: 3 AND2, 2 OR2 not quite! Why?yxxyfdcyabxdcbdcaabdabcf
15Decomposition Example 2Multi-level logic can be less expensiveOriginal formAfter identifying the sub-expressionsdxdxdxzcxcxcxxbababax22211121dcbadcbadcbadcbadabcdcabcdbabcdaz
16Extraction Example 1Having multi-level and multi-output optimization may be advantageousOriginal form2 levels, 6 product terms, 24 transistors in static CMOS implementation (not counting inverters)After extraction:3 levels, 20 transistors in static CMOS implementation (not counting inverters)

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