1EE/CE 6301: Advanced Digital LogicBill SwartzDept. of EEUniv. of Texas at DallasEEDG/CE6301 –B. Swartz
2Multi-Level OptimizationSession 07Adapted from the work of M Nourani to whom I am grateful
3Motivation for Multi-Level Optimization
4General Form•General circuits may have—Sums within products—Products within sums—Arbitrary depth•Example: z=((a.(b+c)+e).f.g+h).i
5Example –Two-Level vs. Multi-Level•Consider the minimal 2-level SOP form—# AND3 = 6; # OR7 = 1 → Total = 7 gates—# gate inputs = 25•This can be improved if we replace the 2-level form with a multi-level, factored form…—# AND3 = 1; # OR2 = 2; # OR3 = 1 → Total = 4 gates!—# gate inputs = 10deyZfgabcxfydexabcgZadfaefbdfbefcdfcefgZadaebdbecdcefgZabc dabc efgZabcdefg
6Consideration of Cost•Two-level implementation for most practical circuits will be too expensive.—Example: 16-bit adder (32 bits inputs, huge number 216to 232product terms)•Two-level is natural for Programmable Logic Array (PLA). Inefficient, hence folded PLAs.•Many of datapath logic are designed by integrating/interfacing modules. A multi-level architecture will be created.
15Decomposition –Example 2•Multi-level logic can be less expensive•Original form•After identifying the sub-expressionsdxdxdxzcxcxcxxbababax22211121dcbadcbadcbadcbadabcdcabcdbabcdaz
16Extraction –Example 1•Having multi-level and multi-output optimization may be advantageous•Original form—2 levels, 6 product terms, 24 transistors in static CMOS implementation (not counting inverters)•After extraction:—3 levels, 20 transistors in static CMOS implementation (not counting inverters)