370L11 - 11. Basic Processor Design: Multi-Cycle Datapath...

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1 © V. Bertacco & D. Winsor, 2007 The material in this presentation cannot be copied in any form without our written permission Prof. Valeria Bertacco & Prof. Don Winsor EECS 370 – Introduction to Computer Organization – Fall 2007 EECS Department University of Michigan in Ann Arbor, USA 11. Basic Processor Design: Multi-Cycle Datapath EECS 370: Introduction to Computer Organization 2/41 The University of Michigan © V. Bertacco & D. Winsor – 2007 From Last Time - What’s Wrong with Single Cycle? 1 ns – Register read/write time 2 ns – ALU/adder 2 ns – memory access 0 ns – MUX, PC access, sign extend, ROM add: 2ns + 1ns + 2ns + 1ns = 6 ns beq: 2ns + 1ns + 2ns = 5 ns sw: 2ns + 1ns + 2ns + 2ns = 7 ns lw: 2ns + 1ns + 2ns + 2ns + 1ns = 8 ns Get read ALU mem write Instr reg oper. reg
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2 EECS 370: Introduction to Computer Organization 3/41 The University of Michigan © V. Bertacco & D. Winsor – 2007 From Last Time - Computing Execution Time ± Assume: 100 instructions executed 25% of instructions are loads, 10% of instructions are stores, 45% of instructions are adds, and 20% of instructions are branches. ± Single-cycle execution: 100 * 8ns = 800 ns ± Optimal execution: 25*8ns + 10*7ns + 45*6ns + 20*5ns = 640 ns EECS 370: Introduction to Computer Organization 4/41 The University of Michigan © V. Bertacco & D. Winsor – 2007 Multiple-Cycle Execution ± Each instruction takes multiple cycles to execute Cycle time is reduced Slower instructions take more cycles Can reuse datapath elements each cycle ± What is needed to make this work? Since you are re-using elements for different purposes, you need more and/or wider MUXes. You may need extra registers if you need to remember an output for 1 or more cycles. Control is more complicated since you need to send new signals on each cycle.
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3 Cycle 1 Cycle 2 Cycle 3 PC Instruction memory Register file Data memory Control ROM M U X M U X M U X M U X Sign extend + 1 + A L U 3x8 decoder R/W En En 6/41 Reg en IR en PC Memory Register file M U X M U X M U X Sign extend A L U R/W En En M U X M U X Instruction Reg Control Multicycle LC2Kx Datapath addr data En En PC en MUX addr Mem en Mem r/w MUX dest MUX rdata MUX alu2 MUX alu1 ALU op 1 0 ALU result
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4 EECS 370: Introduction to Computer Organization 7/41 The University of Michigan © V. Bertacco & D. Winsor – 2007 State Machine for Multi-cycle Control Signals (transition functions) State 0: Fetch cycle beq cycle3 sw cycle3 lw cycle3 add cycle 3 add cycle 4 State1: decode lw cycle4 sw cycle4 beq cycle4 nand cycle 3 nand cycle 4 lw cycle5 2 3 4 5 6 7 9 10 11 12 8 EECS 370: Introduction to Computer Organization 8/41 The University of Michigan © V. Bertacco & D. Winsor – 2007 Implementing the control FSM D Q Current state Implement transition functions (using a ROM and combinational circuits) Inputs: opcode Outputs: 12 bits Next state 4-bit state
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5 9/41 Building the Control Rom 4 × 16 Decoder Output: Control Signals Next State PC en MUX addr Mem r/w IR dest rdata Reg alu1 alu2 ALU op Current State
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This note was uploaded on 04/02/2008 for the course EECS 370 taught by Professor Bertacco during the Winter '08 term at University of Michigan.

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370L11 - 11. Basic Processor Design: Multi-Cycle Datapath...

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