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370L11 - 11 Basic Processor Design Multi-Cycle Datapath...

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1 © V. Bertacco & D. Winsor, 2007 The material in this presentation cannot be copied in any form without our written permission Prof. Valeria Bertacco & Prof. Don Winsor EECS 370 – Introduction to Computer Organization – Fall 2007 EECS Department University of Michigan in Ann Arbor, USA 11. Basic Processor Design: Multi-Cycle Datapath EECS 370: Introduction to Computer Organization 2/41 The University of Michigan © V. Bertacco & D. Winsor – 2007 From Last Time - What’s Wrong with Single Cycle? 1 ns – Register read/write time 2 ns – ALU/adder 2 ns – memory access 0 ns – MUX, PC access, sign extend, ROM add: 2ns + 1ns + 2ns + 1ns = 6 ns beq: 2ns + 1ns + 2ns = 5 ns sw: 2ns + 1ns + 2ns + 2ns = 7 ns lw: 2ns + 1ns + 2ns + 2ns + 1ns = 8 ns Get read ALU mem write Instr reg oper. reg
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