370L10 - 10 Basic Processor Design Single-Cycle and Multi-Cycle Datapaths EECS 370 Introduction to Computer Organization Fall 2007 Prof Valeria

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1 © V. Bertacco & D. Winsor, 2007 The material in this presentation cannot be copied in any form without our written permission Prof. Valeria Bertacco & Prof. Don Winsor EECS 370 – Introduction to Computer Organization – Fall 2007 EECS Department University of Michigan in Ann Arbor, USA 10. Basic Processor Design: Single-Cycle and Multi-Cycle Datapaths 2/26 LC2Kx Datapath Implementation PC Instruction memory Register file Data memory Control ROM M U X M U X M U X M U X Sign extend + 1 + A L U 3x8 decoder R/W En En Instruction bits 15-0 21-19 18-16 24-22 18-16 2-0
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2 3/26 Executing an ADD Instruction PC Instruction memory Register file Data memory Control ROM M U X M U X M U X M U X Sign extend + 1 + A L U 3x8 decoder R/W En En Instruction bits 15-0 21-19 18-16 24-22 18-16 2-0 add regA, regB, destR destR = regA + regB PC = PC + 1 4/26 Executing an ADD Instruction on LC2Kx Datapath PC Instruction memory Register file Data memory M U X M U X M U X M U X Sign extend + 1 + A L U 3x8 decoder add 1 2 3 0 0 1 0 1 0 11 1 1 0 0 0 1 1 0 0 0 R/W En En U
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3 5/26 Executing a NAND Instruction PC Instruction memory Register file Data memory Control ROM M U X M U X M U X M U X Sign extend + 1 + A L U 3x8 decoder R/W En En Instruction bits 15-0 21-19 18-16 24-22 18-16 2-0 nand regA, regB, destR destR = ~(regA & regB) PC = PC + 1 6/26 Executing NAND Instruction on LC2Kx Datapath PC Instruction memory Register file Data memory M U X M U X M U X M U X Sign extend + 1 + A L U 3x8 decoder nand 1 2 3 11 1 1 1 0 0 0 1 0 1 0 0 1 1 0 0 1 R/W En En U
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4 7/26 Executing a LW Instruction PC Instruction memory Register file Data memory Control ROM M U X M U X M U X M U X Sign extend + 1 + A L U 3x8 decoder R/W En En Instruction bits 15-0 21-19 18-16 24-22 18-16 2-0 lw regA, regB, offset regB = M[regA+offset] PC = PC + 1 8/26 Executing a LW Instruction on LC2Kx Datapath PC Instruction memory Register file Data memory M U X M U X M U X M U
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This note was uploaded on 04/02/2008 for the course EECS 370 taught by Professor Bertacco during the Winter '08 term at University of Michigan.

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370L10 - 10 Basic Processor Design Single-Cycle and Multi-Cycle Datapaths EECS 370 Introduction to Computer Organization Fall 2007 Prof Valeria

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