370L13 - 1 V. Bertacco & D. Winsor, 2007 The...

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Unformatted text preview: 1 V. Bertacco & D. Winsor, 2007 The material in this presentation cannot be copied in any form without our written permission Prof. Valeria Bertacco & Prof. Don Winsor EECS 370 Introduction to Computer Organization Fall 2007 EECS Department University of Michigan in Ann Arbor, USA 13. Pipelining: Data Hazards EECS 370: Introduction to Computer Organization 2/43 The University of Michigan V. Bertacco & D. Winsor 2007 Announcements Project 2 Due Friday October 26 5:00 pm (grace period until 11:59pm) Combinations contest entries (submit as 2z) due October 28 Project 3 Available on course webpage this weekend, due November 16 Homework 5 Available on course webpage shortly, due November 8 2 EECS 370: Introduction to Computer Organization 3/43 The University of Michigan V. Bertacco & D. Winsor 2007 Pipelining - What can go wrong? Data hazards : since register reads occur in stage 2 and register writes occur in stage 5 it is possible to read the wrong value if is about to be written. Control hazards : A branch instruction may change the PC, but not until stage 4. What do we fetch before that? Exceptions : How do you handle exceptions in a pipelined processor with 5 instructions in flight? Today - Data hazards What are they? How do you detect them? How do you deal with them? 4/39 PC Inst mem Register file M U X A L U M U X 1 Data memory + + M U X IF/ ID ID/ EX EX/ Mem Mem/ WB M U X Bits 0-2 Bits 16-18 op dest offset valB valA PC+1 PC+1 target ALU result op dest valB op dest ALU result mdata eq? instruction R2 R3 R4 R5 R1 R6 R0 R7 regA regB Bits 22-24 data dest 3 EECS 370: Introduction to Computer Organization 5/43 The University of Michigan V. Bertacco & D. Winsor 2007 Pipeline function for ADD Fetch: read instruction from memory Decode: read source operands from reg Execute: calculate sum Memory: pass results to next stage Writeback: write sum into register file EECS 370: Introduction to Computer Organization 6/43 The University of Michigan V. Bertacco & D. Winsor 2007 Data Hazards add 1 2 3 nand 3 4 5 time fetch decode execute memory writeback fetch decode execute memory writeback add nand If not careful, nand will read the wrong value of R3 Dependency Hazard 4 EECS 370: Introduction to Computer Organization 7/43 The University of Michigan V. Bertacco & D. Winsor 2007 Data Hazards add 1 2 3 nand 3 4 5 time fetch decode execute memory writeback fetch hazard hazard decode execute add nand Assume Register File gives the right value of R3 when read/written during same cycle. This is consistent with the book and the MIPS architecture, but not Project 3....
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370L13 - 1 V. Bertacco & D. Winsor, 2007 The...

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