Lecture17 - Tue sday, May 27 C ck your scoreposting, pick...

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1 Tuesday, May 27 Check your score posting, pick up* Recent scores: Homework #4 *Program #1 *Lab #4 Homework #5 is posted Hardcopy due Thursday (BOC) Solutions will be posted Wednesday evening Lab #5 report is due Friday Last session is at 2:00 today TAs have office hours in the lab Thursday & Friday Program #2 is due Thursday, June 5 Partnership registration due today!
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2 Today's Topics Link Layer Error detection/correction Multi-access protocols (MA) Media Access Control addresses (MAC) Address Resolution Protocol (ARP)
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3 Link Layer Services framing, link access: encapsulate datagram into frame, adding header, trailer channel access if shared medium “MAC” addresses used in frame headers to identify source, dest different from IP address! reliable delivery between adjacent nodes similar to what is done at transport layer rarely used on low bit-error link (fiber, some twisted pair) often used on wireless links: high error rates
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4 Link Layer Services (more) flow control: pacing between adjacent sending and receiving nodes error detection: errors caused by signal attenuation, noise. receiver detects presence of errors: signals sender for retransmission or drops frame error correction: receiver identifies and corrects bit error(s) without resorting to retransmission half-duplex and full-duplex with half duplex, nodes at both ends of link can transmit, but not at same time
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5 Where is the link layer implemented? in all hosts implemented in network adapter (NIC network interface card ) Ethernet card, PCMCI card, 802.11 card implements link, physical layers attaches into host’s system buses combination of hardware, software, firmware handles all link layer functions controller physical transmission cpu memory host bus (e.g., PCI) network adapter card host schematic application transport network link link physical
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6 NIC handles all link layer functions may also handle network/transport layer functions implements direct memory access (DMA) handles buffers, etc. avoids interrupting the CPU unnecessarily sends CPU interrupt when application layer processing is required
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7 NICs Communicating sending side: encapsulates datagram in frame adds error checking bits, reliable data transfer, flow control, etc. receiving side looks for errors, reliable data transfer, flow control, etc extracts datagram and passes it up to next layer controller controller sending host receiving host datagram datagram datagram frame
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8 Error Detection D = Data protected by error checking, may include header fields EDC= Error Detection and Correction bits (redundancy) error detection not 100% reliable larger EDC field yields better detection and correction
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9 Parity Checking Single Bit Parity: Detect single bit errors Two Dimensional Bit Parity : Detect and correct single bit errors ( odd parity ) ( even parity )
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This note was uploaded on 06/28/2009 for the course CS 372 taught by Professor Leviet during the Fall '07 term at Oregon State.

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Lecture17 - Tue sday, May 27 C ck your scoreposting, pick...

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