Lecture11 - Wednesday, April 22 Quiz #1 Project #2 Scores...

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Unformatted text preview: Wednesday, April 22 Quiz #1 Project #2 Scores are posted Pick up Updates? Homework #2 is posted Discussion in class Friday Take the COE Computing Services Survey: http://engr.oregonstate.edu/computing/itsurvey.php Today's Topics Page Tables Segmentation Page Table Structure Diagrams are from Silbershatz & Gagne, "Operating System Concepts", Wiley Contiguous Allocation (review) Entire process address space must be contiguous Algorithms: Base Register, Limit Register make address binding simple First Fit Best Fit Worst Fit Fragmentation Project #3 Contiguous allocation Out of synch with lectures Paging Address space of a process can be non contiguous Divide physical memory into fixedsize blocks called frames process is allocated physical memory when available. Divide logical memory into pages size is power of 2, usually between 512 bytes and 8192 bytes Blocks ... same size as frames Paging Keep track of all free frames. To run a program of size n pages, need to No external fragmentation Possible internal fragmentation. Find n free frames and load program. Set up a page table to translate logical to physical addresses. Address Translation Scheme Address generated by CPU is separated into: Page number (p) used as an index into a page table which contains base address of each page in physical memory Page offset (d) combined with base address to define the physical memory address in the memory unit Implementation of Page Table Page table is kept in main memory. Free frame list Pagetable base register (PTBR) points to the page table. Pagetable length register (PTLR) indicates size of the page table. Address Translation Architecture Paging Example Implementation of Page Table In this scheme every data/instruction access requires two memory accesses. Solution: One for the page table and one for the data/instruction. Slow ... associative memory or translation lookaside buffer (TLB) special fastlookup hardware cache Associative Memory (TLB) Page # Frame # Hardware cache Associative lookup is a parallel search (compares all keys simultaneously !) Address translation (P, F) If P is in the TLB, get frame # Otherwise get frame # from page table in memory TLB Lookup = time unit Assume memory cycle time is m microseconds Hit ratio percentage of times that a page number is found in the TLB Effective Access Time Ratio related to number of associative registers. Hit ratio = EAT = ( + m) + ( + 2m)(1 ) = 2m + m = + (2 )m Looked up in Page Table Found in TLB Effective Access Time (EAT) Paging Hardware With TLB Memory Protection Implemented by associating protection bit with each frame. Validinvalid bit attached to each entry in the page table Memory frames Frame size is determined by a computer's architecture Example: 1GiB memory with 4KiB frame size 262,144 frames Memory pages Linux represents every page with a page structure (include/linux/mm_types.h): struct page { unsigned long flags; atomic_t _count; atomic_t _mapcount; union { struct { unsigned long private; struct address_space *mapping; }; }; pgoff_t index; struct list_head lru; void *virtual; }; Page Table Structure Hierarchical Paging Hashed Page Tables Inverted Page Tables Hierarchical Page Tables Break up the logical address space into multiple page tables. Linux uses 3level paging A logical address (on 32bit machine with 4K frame size) is divided into: a page number (20 bits) a page offset (12 bits) The page number is divided into: a 10bit page number. a 10bit offset. Thus, a logical address is as follows: page number page offset d 12 p2 10 TwoLevel Paging Example p1 10 where p1 is an index into the outer page table, and p2 is the displacement within the page of the outer page table. TwoLevel PageTable Scheme Hashed Page Tables Common in address spaces > 32 bits. The logical page number is hashed into a page table. Use hash table to limit the search to one -- or at most a few -- pagetable entries. This page table contains a chain of pages that hash to the same location. Logical page numbers in this chain are compared, searching for a match If a match is found, the corresponding physical frame is extracted. Hashed Page Table Inverted Page Table One entry for each frame in memory. Uses frame number as index Contains the logical address of the page stored in that memory frame, with PID of the process that owns that page. Hardware links frame number to base address of frame Decreases memory needed to store each page table Increases time needed to search the table when a page reference occurs. Inverted Page Table Architecture Segmentation Memorymanagement scheme that supports user view of memory. A program is a collection of segments A segment is a logical unit such as: Main program Procedure Function Method Object Local variables Global variables Common block Stack Symbol table Arrays Segmentation Architecture Logical address consists of two parts: <segmentnumber, offset> Segment table maps twodimensional physical addresses Each table entry has: base contains the starting physical address where the segment resides in memory limit specifies the length of the segment Segmentation Architecture (Cont.) Protection. With each entry in segment table associate: Protection bits associated with segments validation bit (if 0 illegal segment) read/write/execute privileges Segments vary in length code sharing occurs at segment level. memory allocation is a dynamic storage allocation problem. Example of Segmentation Questions? Do Homework #2 Read Love Chapters 14, 15 ...
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This note was uploaded on 06/28/2009 for the course CS 411 taught by Professor Staff during the Spring '08 term at Oregon State.

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