# lab 4 - The University of Texas at Dallas Computer Science...

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The University of Texas at Dallas Computer Science Department CS2110: Introduction to Digital System Laboratory Experiment #4 – Familiarization with Bistable Circuits (Flip-Flops or Latches) 1. Introduction: In laboratory exercises #’s 1-3, we became familiar with logic gates which represented the six fundamental Boolean functions (NAND/AND, NOR/OR, XOR, and NOT) and with the binary adder circuit. In this laboratory we will study another type of logic function that we have discussed in class – the bistable multivibrator , or flip-flop. Simple logic gates, such as we have studied so far, are referred to as combinational logic . Such logic circuits have outputs that depend only on their inputs. Thus, the output of a combinational logic circuit changes state as soon as the input stimulus is changed. Bistable circuits, on the other hand, may maintain their internal state, under certain conditions (and so long as power is available to the circuit) even when the input stimulus is changed. Bistable circuits are representative of the class of sequential logic . We will investigate the behavior of simple bistable circuits today. 2. Goal of this exercise: The purpose of Experiment #4 is to familiarize students with the functionality of the simple R-S flip-flop (or bistable circuit), with the operation of D and J-K flip-flops, and with the construction of a clocked flip-flop (essentially a clocked D-type FF). We will build the RS and clocked D flip-flop circuits in the lab. 3. Theory of experiment: We have studied various FF circuits in class. The basic types that we will explore today are: R-S FF (built in the lab): Basically an asynchronous circuit whose Q output is activated high (1) by a negative set pulse on the S input and whose Q output is activated high by the R input. Simultaneous low S and R inputs are forbidden (both Q states will be high). D FF: Essentially a clocked FF with only one input; may have asynchronous Preset and Clear. J-K FF: Similar to the clocked R-S FF, except that the circuit is wired so that simultaneous “1” inputs on J and K produce a toggle of the ff to the opposite state rather than an undefined state. Clocked D FF (built in the lab): A variation on the clocked R-S FF in which the R input is created by inverting the S input. In order to demonstrate the circuit mechanics of the R-S FF, we will build the circuit from a simple 74LS00 chip using NAND gates. We will then operate and observe the functionality of the 74LS107 J-K FF and the 74LS74 D FF. Finally, we will construct a clocked D FF from simple gates.

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lab 4 - The University of Texas at Dallas Computer Science...

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