Unformatted text preview: 5. Design 16-bit carry-select adders using (i) 4-bit sections and, again, using (ii) 8-bit sections. Compare gate delay of these two designs. 6. Repeat #5 using 4- and 8-sections of carry look ahead adders instead ripple-carry subcircuits. 7. Design an 4x4 add-shift multiplier and show, step-by-step, how the following numbers are added 0110 1011 x 1010 1001 ------- ------ 8. Design a 4x4 array multiplier and repeat #8. 9. Assuming #8 and #9 use only F/As and ripple-carry-adders, calculate the worst-case delay in each multiplier. 10. Design an 8-bit multiplier using 4-bit (assume a black box) multipliers and (may be) additional logic. First, show how this may be done in a product array....
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This note was uploaded on 07/08/2009 for the course ECEN 248 taught by Professor Lu during the Spring '08 term at Texas A&M.
- Spring '08