Ecen 248 HW5

Ecen 248 HW5 - 5. Design 16-bit carry-select adders using...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
ELEN 248: Assignment #5 1. Perform the following additions and subtractions assumging Sign-magnitude 0011 1010 1101 1110 + 1010 + 1011 - 0101 1010 ------- ------ ------ ------ One’s compliment 0011 1010 1101 1110 + 1010 + 1011 - 0101 1010 ------- ------ ------ ------ Two’s compliment 0011 1010 1101 1110 + 1010 + 1011 - 0101 1010 ------- ------ ------ ------ 2. Implement a combinational logic circuit that converts 4-bit one’s complement numbers into corresponding 4-bit twos compliment numbers 3. Implement a combinational logic circuit that converts 4-bit two’s complement numbers into corresponding 4-bit sign-magnitude numbers (what assumption do you have to make here?) 4. Draw a 1-bit subtractor using one F/A and additional gates
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 5. Design 16-bit carry-select adders using (i) 4-bit sections and, again, using (ii) 8-bit sections. Compare gate delay of these two designs. 6. Repeat #5 using 4- and 8-sections of carry look ahead adders instead ripple-carry subcircuits. 7. Design an 4x4 add-shift multiplier and show, step-by-step, how the following numbers are added 0110 1011 x 1010 1001 ------- ------ 8. Design a 4x4 array multiplier and repeat #8. 9. Assuming #8 and #9 use only F/As and ripple-carry-adders, calculate the worst-case delay in each multiplier. 10. Design an 8-bit multiplier using 4-bit (assume a black box) multipliers and (may be) additional logic. First, show how this may be done in a product array....
View Full Document

Ask a homework question - tutors are online