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180
CHAPTER
5
THE CMOS INVERTER
Quantification of integrity, performance, and energy metrics of an inverter
Optimization of an inverter design
5.1
Exercises and Design Problems
5.2
The Static CMOS Inverter — An Intuitive
Perspective
5.3
Evaluating the Robustness of the CMOS
Inverter: The Static Behavior
5.3.1
Switching Threshold
5.3.2
Noise Margins
5.3.3
Robustness Revisited
5.4
Performance of CMOS Inverter: The Dynamic
Behavior
5.4.1
Computing the Capacitances
5.4.2
Propagation Delay: FirstOrder
Analysis
5.4.3
Propagation Delay from a Design
Perspective
5.5
Power, Energy, and EnergyDelay
5.5.1
Dynamic Power Consumption
5.5.2
Static Consumption
5.5.3
Putting It All Together
5.5.4
Analyzing Power Consumption Using
SPICE
5.6
Perspective: Technology Scaling and its
Impact on the Inverter Metrics
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Exercises and Design Problems
181
5.1
Exercises and Design Problems
1.
[M, SPICE, 3.3.2] The layout of a static CMOS inverter is given in Figure 5.1. (
λ
=0
.125
μm).
a.
Determine the sizes of the NMOS and PMOS transistors.
b.
Plot the VTC (using HSPICE) and derive its parameters (
V
OH
,
V
OL
,
V
M
,
V
IH
,and
V
IL
).
c.
Is the VTC affected when the output of the gates is connected to the inputs of 4 similar
gates?.
d.
Resize the inverter to achieve a switching threshold of approximately 0.75 V. Do not lay
out the new inverter, use HSPICE for your simulations. How are the noise margins
affected by this modification?
2.
Figure 5.2 shows a piecewise linear approximation for the VTC. The transition region is
approximated by a straight line with a slope equal to the inverter gain at
V
M
. The intersection
of this line with the
V
OH
and the
V
OL
lines defines
V
IH
and
V
IL
.
a.
The noise margins of a CMOS inverter are highly dependent on the sizing ratio,
r
=
k
p
/
k
n
,
of the NMOS and PMOS transistors. Use HSPICE with
V
Tn
=

V
Tp
 to determine the value
of
r
that results in equal noise margins? Give a qualitative explanation.
b.
Section 5.3.2 of the text uses this piecewise linear approximation to derive simplified
expressions for
NM
H
and
NM
L
in terms of the inverter gain. The derivation of the gain is
based on the assumption that both the NMOS and the PMOS devices are velocity saturated
at
V
M
. For what range of
r
is this assumption valid? What is the resulting range of
V
M
?
c.
Derive expressions for the inverter gain at
V
M
for the cases when the sizing ratio is just
above and just below the limits of the range where both devices are velocity saturated.
What are the operating regions of the NMOS and the PMOS for each case? Consider the
effect of channellength modulation by using the following expression for the smallsignal
resistance in the saturation region:
r
o,sat
=1
/
(λ
I
D
).
Figure 5.1
CMOS inverter layout.
In
Out
GND
V
DD
=2.5V
.
Poly
Metal1
NMOS
PMOS
Poly
Metal1
2
λ
182
THE CMOS INVERTER
Chapter 5
3.
[M, SPICE, 3.3.2] Figure 5.3 shows an NMOS inverter with resistive load.
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This note was uploaded on 07/09/2009 for the course ECE 4740 taught by Professor Bhave during the Spring '08 term at Cornell University (Engineering School).
 Spring '08
 Bhave

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