1
Chapter 7 Problem Set
Chapter 7
PROBLEMS
1.
[M, None, 7.4] Figure 1 shows a practical implementation of a pulse register.
Clock
Clk
is
ideal with 50% duty cycle.
Data :
V
DD
= 2.5V,
t
p,inv
= 200ps, node capacitances are
C
Clkd
= 10fF,
C
x
= 10fF, both true and
complementary outputs node capacitances are 20fF.
a.
Draw the waveforms at nodes
Clk
,
Clkd
,
X
and
Q
for two clock cycles, with
D
= 0 in one
cycle and
D
= 1 in the other.
b.
What is the approximate value of setup and hold times for this circuit?
c.
c)If the probability that
D
will change its logic value in one clock cycle is
α
, with equal
probability of being 0 or 1, what is the power consumption of this circuit? (exclude the
power consumption in the clock line)
f
clk
= 100 MHz.
V
DD
X
Clk
D
Clkd
Q
Q
Figure 0.1
Pulse register.
chapter7ex.fm
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2
Chapter 7 Problem Set
2.
[M, None, 7.4] Figure 2 shows a register that attempts to statistically reduce power consump
tion using a datatransition lookahead technique.
a.
Briefly describe the operation of the circuit.
b.
If all the NMOS transistors are of the same size, and all of the PMOS transistors are of the
same size, two times wider than the NMOS, roughly determine the input switching proba
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 Spring '08
 Bhave
 Integrated Circuit, Multivibrator, Flipflop, Relaxation oscillator, Schmitt

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