chapter11_ex

chapter11_ex - second-chapter11-ex.fm Page 1 Friday October...

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1 Chapter 11 Problem Set Chapter 11 PROBLEMS 1. [E, None, 11.6] For this problem you are given a cell library consisting of full adders and two- input Boolean logic gates (i.e. AND, OR, INVERT, etc.). a. Design an N-bit two's complement subtracter using a minimal number of Boolean logic gates. The result of this process should be a diagram in the spirit of Figure 11.5 . Specify the value of any required additional signals (e.g., C in ). b. Express the delay of your design as a function of N , t carry , t sum , and the Boolean gate delays ( t and , t or , t inv , etc.). 2. [M, None, 11.6] A magnitude comparator for unsigned numbers can be constructed using full adders and Boolean logic gates as building blocks. For this problem you are given a cell library consisting of full adders and arbitrary fan-in logic gates (i.e., AND, OR, INVERTER, etc.). a. Design an N -bit magnitude comparator with outputs and A = B using a minimal number of Boolean logic gates. The result of this process should be a diagram in the spirit of Figure 11.5. Specify the value of any required control signals (e.g., C in ). Express the delay of your design in computing the two outputs as a function of N , t carry , t sum , and the Boolean gate delays ( t and , t or , t inv , etc.).3. 3. [E, None, 11.6] Show how the arithmetic module in Figure 0.1 can be used as a comparator. Derive an expression for its propagation delay as a function of the number of bits. 4. [E, None, 11.6] The circuit of Figure 11.2 implements a 1-bit datapath function in dynamic (precharge/evaluate) logic. a. Write down the Boolean expressions for outputs F and G . On which clock phases are out- puts F and G valid? To what datapath function could this unit be most directly applied (e.g., addition, subtrac- tion, comparison, shifting)? 5. [M, None, 11.3] Consider the dynamic logic circuit of Figure 0.2 . a. What is the purpose of transistor M 1 ? Is there another way to achieve the same effect, but with reducing capacitive loading on the clock Φ ? AB Figure 0.1 Arithmetic module. a i a i b j b j c j d j c j +1 d j+1 c 0 c 1 d 0 d 1 c 1 c 2 d 1 d 2 c 2 c 3 d 2 d 3 c 3 c 4 d 3 d 4 a 0 b 0 a 1 b 1 a 2 b 2 a 3 b 3 second-chapter11-ex.fm Page 1 Friday, October 3, 2003 9:48 PM
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2 Chapter 11 Problem Set b. How can the evaluation phase of F be sped up by rearranging transistors? No transistors should be added, deleted, or resized. c. Can the evaluation of G be sped up in the same manner? Why or why not? 6. [M, SPICE, 11.3] The adder circuit of Figure 0.3 makes extensive use of the transmission gate XOR. V DD = 2.5 V. a. Explain how this gate operates. Derive the logic expression for the various circuit nodes. Why is this a good adder circuit? Derive a first-order approximation of the capacitance on the C o -node in equivalent gate- capacitances. Assume that gate and diffusion capacitances are approximately identical.
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