ikiuccevap

# ikiuccevap - UNIVERSITY OF CALIFORNIA College of...

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Problem 1 – Static Registers, Sizing, and Timing For a particular instance of the register shown in Figure 1, the source driver for input D is an inverter. Assume the cross-coupled inverters are all minimum-sized (Wp=2Wn), Figure 1. Static register. a. Find a sizing constraint on the source inverter and transmission gate that ensures proper functionality for storing a “0” (ignore body effect) (Hint: size the pull- down of the driving inverter the same as the pass-transistor gate). The driving stage and pass transistor must be able to bring the input of the top inverter below its switching point in order to store a zero. During this transition, there is a direct path between VDD and ground through the series combination of the inverter NMOS and pass gate, and the PMOS in the bottom feedback inverter (figure 2b). To simplify the analysis, we assume the PMOS remains fully on (ignore the feedback, which makes our constraint slightly tighter than necessary). Assuming 0.25um technology, and Vdd=2.5, the switching point for the inverter will be Vm=1.25V. Ignoring body effect. UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 7, 2002 by Henry Jen and Stanley Wang ([email protected]) Borivoje Nikolic Homework #9 EECS 141

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Vx Figure 1b. Path of contention. Vx was originally at Vdd and is now pulled down to Vdd/2 I driving stage = I pass transistor = I feedback inverter ,and assume (W/L) driving stage = (W/L) pass transistor The two NMOS transistors can be modeled as one NMOS with twice the length. kp’(W/L) p V dsatp (Vdd-Vtp-|V dsatp |/2) = kn’(W/2L) n V dsatn (Vdd-Vtn-V dsatn /2) (W/L)n / (W/L)p > 0.75, so (W/L) pass transistor = (W/L) driving stage = 2*0.75(W/L) nmos = 1.5(W/L) nmos b. How might you redesign the register to relax the sizing requirement on the driving stage? In order to make the driving stage smaller, we must weaken the feedback inverters.
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