ilksorununcevabi - UNIVERSITY OF CALIFORNIA College of...

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UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 19, 2006 by Karl Skucha ([email protected]) Borivoje Nikolić Homework #9 EE 141 Problem #1: Power in CMOS Let’s evaluate the effect of logic choice on power dissipation. Circuit A is an AND4 implemented as a NAND2 chain while Circuit B implements the same function using a 4 input gate. a) Size circuit A and circuit B for minimum delay with Cin of 3fF and Cout of 50fF. Report your answer in terms of the input capacitance seen at each gate. Circuit A H=50/3 * (4/3) 3 =39.51 h=H 1/6 =1.845 G1 G2 G3 G4 G5 G6 3fF 4.15fF 7.66fF 10.60fF 19.55fF 27.06fF 50 fF A B C D Circuit A A B C D 50 fF Circuit B G1 G2 G3 G1 G4 G5 G6 G2
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Circuit B H=50/3 * (6/3) = 33.33 H=H 1/2 =5.77 G1=3fF G2=8.66fF b) Given that P(A=1) = P(B=1) = P(C=0) = P(D=0) = 0.25, calculate the probability of energy consuming transitions P(0 → 1) at the outputs of the gates in both circuits. Circuit A P(0→1) = P(0) * P(1) = (1-P(0)) * P(0) In1 In2 Out 0 (x) 0 (y) 1 (xy) 0 (x) 1 (1-y) 1 (x-xy) 1 (1-x) 0 (y) 1 (y-xy) 1 (1-x) 1 (1-y) 0 (1-y-x+xy) NAND2 Truth Table with Probabilities P(0) = 1-y-x+xy P(1) = x+y-xy
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This note was uploaded on 07/09/2009 for the course ECE 4740 taught by Professor Bhave during the Spring '08 term at Cornell University (Engineering School).

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ilksorununcevabi - UNIVERSITY OF CALIFORNIA College of...

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