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chapter1_ex - amount of very interesting information 3[D...

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11 CHAPTER 1 INTRODUCTION n The evolution of digital circuit design n Compelling issues in digital circuit design n How to measure the quality of a design Valuable references 1.1 A Historical Perspective 1.2 Issues in Digital Integrated Circuit Design 1.3 Quality Metrics of a Digital Design 1.4 Summary 1.5 To Probe Further
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12 INTRODUCTION Chapter 1 Exercises 1. [E, None, 1.2] Based on the evolutionary trends described in the chapter, predict the integra- tion complexity and the clock speed of a microprocessor in the year 2015. Determine also how much DRAM should be available on a single chip at that point in time, if Moore’s law would still hold. 2. [D, None, 1.2] Visit the Intel on-line microprocessor museum ( http://www.intel.com/intel/intelis/museum/exhibit/hist_micro/index.htm ). While browsing through the microprocessor hall-of-fame, determine the rate of increase in transistor counts and clock frequencies in the 70’s, 80’s, and 90’s. Also, create a plot of the number of transis- tors versus technology feature size. Spend some time browsing the site. It contains a large
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Unformatted text preview: amount of very interesting information. 3. [D, None, 1.2] By scanning the literature, find the leading-edge devices at this point in time in the following domains: microprocessor, signal processor, SRAM, and DRAM. Determine for each of those, the number of integrated devices, the overall area and the maximum clock speed. Evaluate the match with the trends predicted in section 1.2. 4. [D, None, 1.2] Find in the library the latest November issue of the Journal of Solid State Cir-cuits. For each of the papers, determine its application class (such as microprocessor, signal processor, DRAM, SRAM), the type of manufacturing technology used (MOS, bipolar, etc.), the minimum feature size, the number of devices on a single die, and the maximum clock speed. Tabulate the results along the various application classes. 5. [E, None, 1.2] Provide at least three examples for each of the abstraction levels described in Figure 1.6. More to come in the very near future!...
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