chapter3_ex

# chapter3_ex - 1 Chapter 3 Problem Set Chapter 3 PROBLEMS...

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1 Chapter 3 Problem Set Chapter 3 PROBLEMS For all problems, use the device parameters provided in Chapter 3 (Tables 3.2 and 3.5) and the inside back book cover, unless otherwise mentioned. Also assume T = 300 K by default. 1. [E,SPICE,3.2.2] a. Consider the circuit of Figure 0.1. Using the simple model, with V Don = 0.7 V, solve for I D . b. Find I D and V D using the ideal diode equation. Use I s = 10 –14 A and T = 300 K. c. Solve for V D 1 , V D 2 , and I D using SPICE. d. Repeat parts b and c using I S = 10 –16 A , T = 300K, and I S =10 –14 A, T = 350 K. 2. [M, None, 3.2.3] For the circuit in Figure 0.2, V s = 3.3 V. Assume A D = 12 µ m 2 , φ 0 = 0.65 V, and m = 0.5. N A = 2.5 E16 and N D = 5 E15. a. Find I D and V D . b. Is the diode forward- or reverse-biased? c. Find the depletion region width, W j , of the diode. d. Use the parallel-plate model to find the junction capacitance, C j . e. Set V s = 1.5 V. Again using the parallel-plate model, explain qualitatively why C j increases. 3. [E, None, 3.3.2] Figure 0.3 shows NMOS and PMOS devices with drains, source, and gate ports annotated. Determine the mode of operation (saturation, linear, or cutoff) and drain cur- rent I D for each of the biasing configurations given below. Verify with SPICE. Use the follow- ing transistor data: NMOS: k' n = 115 µ A/V 2 , V T 0 = 0.43 V, λ = 0.06 V –1 , PMOS: k' p = 30 µ A/V 2 , V T 0 = –0.4 V, λ = -0.1 V –1 . Assume ( W/L ) = 1. a. NMOS: V GS = 2.5 V, V DS = 2.5 V. PMOS: V GS = –0.5 V, V DS = –1.25 V. b. NMOS: V GS = 3.3 V, V DS = 2.2 V. PMOS: V GS = –2.5 V, V DS = –1.8 V. c. NMOS: V GS = 0.6 V, V DS = 0.1 V. PMOS: V GS = –2.5 V, V DS = –0.7 V. 4. [E, SPICE, 3.3.2] Using SPICE plot the I-V characteristics for the following devices. Figure 0.1 Resistor diode circuit. R 1 = 2k I D + 2.5 V R 2 = 2k + V D + V s =3.3V R s = 2 k V D Figure 0.2 Series diode circuit I D +

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2 Chapter 3 Problem Set a. NMOS W = 1.2μm, L = 0.25μm b. NMOS W = 4.8μm, L = 0.5μm c. PMOS W = 1.2 μm, L = 0.25 μm d. PMOS W = 4.8 μm, L = 0.5 μm 5. [E, SPICE, 3.3.2] Indicate on the plots from problem 4. a. the regions of operation. b. the effects of channel length modulation. c. Which of the devices are in velocity saturation? Explain how this can be observed on the I- V plots. 6. [M, None, 3.3.2] Given the data in Table 0.1 for a short channel NMOS transistor with V DSAT = 0.6 V and k =100 µ A/V 2 , calculate V T 0 , γ , λ , 2| φ f |, and W/L : 7. [E, None, 3.3.2] Given Table 0.2 ,the goal is to derive the important device parameters from these data points. As the measured transistor is processed in a deep-submciron technology, the unified model ’ holds. From the material constants, we also could determine that the satura- tion voltage V DSAT equals -1V. You may also assume that -2 Φ F = -0.6V. NOTE: The parameter values on Table 3.3 do NOT hold for this problem. a. Is the measured transistor a PMOS or an NMOS device? Explain your answer. b. Determine the value of V T0 . c. Determine γ . d. Determine λ . Table 0.1 Measured NMOS transistor data V GS V DS V BS I D ( μA ) 1 2 .
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chapter3_ex - 1 Chapter 3 Problem Set Chapter 3 PROBLEMS...

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