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Chapter 4 Problem Set
Chapter 4
Problems
1.
[M, None, 4.x] Figure 0.1 shows a clockdistribution network. Each segment of the clock net
work (between the nodes) is 5 mm long, 3
µ
m wide, and is implemented in polysilicon. At
each of the terminal nodes (such as
R
) resides a load capacitance of 100 fF.
a.
Determine the average current of the clock driver, given a voltage swing on the clock lines
of 5 V and a maximum delay of 5 nsec between clock source and destination node
R
. For
this part, you may ignore the resistance and inductance of the network
b.
Unfortunately the resistance of the polysilicon cannot be ignored. Assume that each
straight segment of the network can be modeled as a
Π
network. Draw the equivalent cir
cuit and annotate the values of resistors and capacitors.
c.
Determine the dominant timeconstant of the clock response at node
R
.
2.
[C, SPICE, 4.x] You are designing a clock distribution network in which it is critical to mini
mize skew between local clocks (
CLK
1,
CLK
2, and
CLK
3). You have extracted the
RC
net
work of Figure 0.2, which models the routing parasitics of your clock line. Initially, you
notice that the path to
CLK
3 is shorter than to
CLK
1 or
CLK
2. In order to compensate for this
imbalance, you insert a transmission gate in the path of
CLK
3 to eliminate the skew.
a.
Write expressions for the timeconstants associated with nodes
CLK
1,
CLK
2 and
CLK
3.
Assume the transmission gate can be modeled as a resistance
R
3
.
b.
If
R
1
=
R
2
=
R
4
=
R
5
=
R
and
C
1
=
C
2
=
C
3
=
C
4
=
C
5
=
C
, what value of
R
3
is required to
balance the delays to
CLK
1,
CLK
2, and
CLK
3?
c.
For
R
=
750
Ω
and
C
=
200fF, what (
W
/
L
)’s are required in the transmission gate to elimi
nate skew? Determine the value of the propagation delay.
d.
Simulate the network using SPICE, and compare the obtained results with the manually
obtained numbers.
3.
[M, None, 4.x]Consider a CMOS inverter followed by a wire of length
L
. Assume that in the
reference design, inverter and wire contribute equally to the total propagation delay
t
pref
. You
may assume that the transistors are velocitysaturated. The wire is scaled in line with the
ideal
wire scaling model
. Assume initially that the wire is
a local wire
.
a.
Determine the new (total) propagation delay as a a function of
t
p
ref
, assuming that technol
ogy and supply voltage scale with a factor 2. Consider only firstorder effects.
b.
Perform the same analysis, assuming now that the wire scales a
global wire
, and the wire
length scales inversely proportional to the technology.
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 Spring '08
 Bhave

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