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chapter10_ex - 1 Chapter 10 Problem Set Chapter 10 PROBLEMS...

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1 Chapter 10 Problem Set Chapter 10 PROBLEMS 1. [C, None, 9.2] For the circuit in Figure 0.1, assume a unit delay through the Register and Logic blocks (i.e., t R = t L = 1). Assume that the registers, which are positive edge-triggered, have a set-up time t S of 1. The delay through the multiplexer t M equals 2 t R . a. Determine the minimum clock period. Disregard clock skew. b. Repeat part a, factoring in a nonzero clock skew: δ = t θ t θ = 1 . c. Repeat part a, factoring in a non-zero clock skew: δ = t θ t θ = 4 . d. Derive the maximum positive clock skew that can be tolerated before the circuit fails. e. Derive the maximum negative clock skew that can be tolerated before the circuit fails. 2. This problem examines sources of skew and jitter. a. A balanced clock distribution scheme is shown in Figure 0.2. For each source of variation, identify if it contributes to skew or jitter. Circle your answer in Table 0.1 Figure 0.1 Sequential circuit. Register Mux Logic t θ t θ Θ Clock Generation Devices Power Supply Noise Interconnect Data Dependent Load Static Temperature Gradient 6 1 2 3 4 5 Figure 0.2 Sources of Skew and Jitter in Clock Distribution.
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2 Chapter 10 Problem Set b. Consider a Gated Clock implementation where the clock to various logical modules can be individually turned off as shown in Figure 0.3. (i.e., Enable 1 ,..., Enable N can take on dif- ferent values on a cycle by cycle basis). Which approach ( A or B ) results in lower jitter at the output of the input clock driver? (hint: consider gate capacitance) Explain. 3. Figure 0.4 shows a latch based pipeline with two combinational logic units. 1) Uncertainty in the clock generation circuit Skew Jitter 2) Process variation in devices Skew Jitter 3) Interconnect variation Skew Jitter 4) Power Supply Noise Skew Jitter 5) Data Dependent Load Capacitance Skew Jitter 6) Static Temperature Gradient Skew Jitter Table 0.1 Sources os Skew and Jitter V DD Clk Enable Clk Enable Gated Clock V DD Clk Enable Clk Enable Gated Clock Gating Approach A Gating Approach B Clk Enable 1 Enable 2 Enable N Input Driver Fine-grain Clock Gating Clock Figure 0.3 Jitter in clock gating D Q CL 1 80ns CL 2 30ns a c e D Q d I CLK CLK b Figure 0.4 Latch Based Pipeline D Q
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Digital Integrated Circuits - 2nd Ed 3 Recall that the timing diagram of a combinational logic block and a latch can be drawn as follows, where the shaded region represents that the data is not ready yet. Assume that the contamination delay t cd of the combinational logic block is zero, and the t clk-q of the latch is zero too. a. Assume the following timing for the input I . Draw the timing diagram for the signals a, b, c, d and e . Include the clock in your drawing. b. State the deadline for the computation of the signal b and d , i.e. when is the latest time they can be computed, relative to the clock edges. In your diagram for (a), label with a “< >” the “slack time” that the signals b and d are ready before the latest time they must be ready.
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This note was uploaded on 07/09/2009 for the course ECE 4740 taught by Professor Bhave during the Spring '08 term at Cornell.

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chapter10_ex - 1 Chapter 10 Problem Set Chapter 10 PROBLEMS...

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