Chapter 12
PROBLEMS
1.
[E, SPICE, 12.2.1] Use SPICE to compute the access time of the 512
⋅
512 NOR ROM of Example
12.4.
Use a simplified model
(i.e., do not include all the transistors but model their impact on word and
bit lines). Compare the obtained results (row, column, and overall delay) with the results of the hand
analysis.
2.
[E, None, 12.2.3] For a memory containing a 4096 word
⋅
2048 bit array of SRAM cells with a
differential bitline architecture, assume that the dynamic power consumption is dominated by charging
and discharging the bit lines. Assume further that the cells are tiled at a vertical pitch of 5
µ
m and a
horizontal pitch of 3
µ
m. Also assume that each cell adds a load of 3 fF to
BL
and
BL’
. Bit lines are in
metal1 and are 0.6
µ
m wide.
a.
Compute the capacitance loading each bit line. Break it down into contributions from wiring and
from memory cells.
b.
If the bit lines are precharged to 1.25 V and are allowed to develop a maximum differential voltage
of 1 V (symmetric around the precharge voltage) during a read operation, what is the power
consumption by the memory while reading at an access rate of 5 MHz.
3.
[E, None, 12.2.3] Using the result of Eq. (12.3) and the device parameters of Table 32, construct a plot
of
∆
V/V
Tn
vs. V
DD
for an SRAM with a cell ratio of 1. Discuss the effect of supply voltage scaling on
read upset malfunction.
4.
[M, None, 12.2.3] Consider the sixtransistor NMOS static memory cell of Figure 12.85 . You may
ignore the body effect for this problem (
γ
= 0). Use (
W
/
L
)
2
= 1.2/24 and (
W
/
L
)
3
= 2.4/1.2. The threshold
voltage
V
TO
of the depletion transistors equals –2 V. Assume Vdsat > Vdd (long channel device).
a.
Assume first that node
Q
is in the 1 state and node
Q
is 0. In order to write a 0 to node
Q
, bit line
BL
is lowered to 0.9 V. Determine the minimal size of transistor
M
1
so that the cell just flips when
this voltage is reached. Assume that the switching threshold
V
M
of the NMOS inverter equals 0.92
V.
b.
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 Spring '08
 Bhave
 Transistor, µm, bit line, bit lines, read operation, bit line BL

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