lab3_2008 - CARLETON UNIVERSITY ELEC-3500 Department of...

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Unformatted text preview: CARLETON UNIVERSITY ELEC-3500 Department of Electronics Digital Electronics November 13, 2006 CMOS Sequential Logic Gates Design and Specification of Sequential Logic Gates and Library Cell Digital designs are composed of combinational logic (gates like INV, NAND and NOR) and sequential elements which contain memory (Flip-Flops and latches). Be warned, do NOT use latches in real life. The ONLY exception is in the lab below where you build a flip-flop out of two latches for educational purposes. In this lab you will first build a MUX, then use it to make a latch and then use the latch to create a flip-flop. The sequence of circuits you will build are: a) The MUX. b) The latch built from a MUX c) The master-slave D flip-flop, made from latches. 1. The Mux The MUX switches an output between two inputs as dictated by a control signal. Here: if(ctrl= =1) y=d; else y=q; Ctrl d q 1 MU X y 1 G1 0.5pF ctrl FIGURE 2.1 Transmission-Gate MUX. A MUX is built out of two of the transmission gates and an inverter. You will need to put voltmeters at ctrl and y. Vd d +2.5 y Vq q V 0.5 V Signal Inputs Set the input waveform Vd = 2V, and Vq = 0.5V. This allows y to be seen to change when the MUX switches from q to d. Ctrl +2.5 ctrl FIGURE 2.2 ctrl Q1. Plot the output waveforms showing the ctrl and y signals. Explain what is happening when the CLK is high and when the CLK is low. Electrical Engineering DIGITAL ELECTRONICS J.Knight 1 Carleton University 97.350, CMOS Sequential Logic Gates , Testing the MUX Determine the propagation delay between the time the ctrl rises and the switched output appears at y. This is called tCHYV (time from Control High to Y Valid). Most of these propagation delays are measured between 50% points. ctrl y tCHYV tRISE tFALL tPULWIDTH tPERIOD tDELAY Make the ctrl rise and fall times fast enough (under 1ns). Otherwise you will be reporting that tCHYV is proportional to the input rise/fall time. The Spice pulse genera- FIGURE 2.3 tor can be set from its attributes as shown in FIGURE 2.3. Q2. Record tCHYV and the similar signal tCLYV (Control Low Y Valid). FIGURE 2.4 MUX made from gates 2. The D-latch Convert the MUX to a D-Latch. FIGURE 2.15b will work for a MUX constructed of gates but not transmission gates. The conservation of energy has everything to do with this. A gate has gain. d ctrl y q FIGURE 2.15b D latch from a MUX Q3. CLK CLK Testing The Latch Make sure your latch functions as a transparent latch. D V d 1D C1 q CLK CLK LATCH FIGURE 2.5 The Setup Time D CLK FIGURE 2.6 T L T L T L T L In order to check the setup time of the latch, one must make d and clk input edges slide past each other. 1. The demonstration Pspice is limited to 10 transistors. You will have to use the inverter made without transistors or use the full Pspice simulator. Electronic Engineering November 13, 2006 page 2, of 4 10K Q4. Sketch part of your test waveform that proves the latch functions as a transparent latch. V 20K What components are added to your D latch (Ref: Figure 2.15b) to make it work with transmission gates.1 Why are they necessary? D d q 1 MU X q 1 G1 V Carleton University 97.350, CMOS Sequential Logic Gates , If the d input changes too close to the CLK edge the d input will not be captured as q. However if the d input is stable at least a setup time before the CLK edge, then a stable value will be captured. CLK d q Setup time approximate Note d was captured as q FIGURE 2.7 Q5. Measure the setup time using your sliding waveforms. You may want to extend the time of the simulation. Show a plot of where you measured the setup time. or The symbol for a transmission gate is Your latch should be as shown in FIGURE 2.8 or FIGURE 2.9. Add a 0.5pf capacitive load to q (not Q) and see if that affects the setup time. D CLK X q 20K FIGURE 2.8 Q6. Measure the new setup time. Comment on it. Commercial latches add an extra inverter as a buffer amplifier to keep the load from influencing the setup time. D Q q Q CLK FIGURE 2.9 The Hold Time The hold time is the length of time the d signal must be stable after the clock changes to be sure of capturing the correct value. Good latches have zero or even a negative hold time. The same sliding waveforms used to measure the setup time can also measure the hold time. CLK d q q FIGURE 2.10 testing for zero hold time Longer hold time needed Zero hold time Less than zero hold time 3. The D Flip-Flop q The master-slave D flip-flop is made by connecting two D latches in series. The two are transparent on opposite clock edges. D TRANSP STORE QM STORE TRANSP QS Q CLK MASTER SECTION FIGURE 2.11 SLAVE SECTION Electrical Engineering November 13, 2006 page 3, of 4 Carleton University 97.350, CMOS Sequential Logic Gates , When the master is high it holds the output and the transparent slave lets it through. When the master goes transparent, the slave holds the previous output so it does not change. This makes the flipflops edge sensitive. It samples the data at the rising or falling edge of the clock. FIGURE 2.12 CLOCK LOW HOLD TRANSP CLOCK HIGH TRANSP HOLD Q7. Measure the setup time of the D flip-flop using the sliding waveform. Deliverables: - Fill out the cover sheet. - Demo your work to a TA. - Answer all questions. Electronic Engineering November 13,2006 page 4, of 4 ...
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This note was uploaded on 07/16/2009 for the course SYSC 3600 taught by Professor John bryant during the Winter '08 term at Carleton CA.

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