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lecture13annotat - 6.012 - Microelectronic Devices and...

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits October 25, 2005 Contents : 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS inverter with current-source pull-up 3. Complementary MOS (CMOS) Inverter Reading assignment: Howe and Sodini, Ch. 5, § 5.3
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-2 Key questions What are the key design trade-offs of the NMOS in- verter with resistor pull-up? How can one improve upon these trade-offs? What is special about a CMOS inverter?
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-3 1. NMOS inverter with resistor pull-up (cont.) V + = V DD V OUT =V DS V OH =V MAX =V DD R I R V OUT V M I D V IN C L V OL =V MIN 0 V OUT =V IN slope= A v (V M ) 0 V T V M V DD V IN =V GS V IL V IH 2 Noise margins: V MAX V M NM L = V IL V OL = V M V MIN | A v ( V M ) | 1 V H = V OH V IH = V V M (1+ )+ | A v ( V M ) | | A v ( V M ) | Need to compute | A v ( V M ) | .
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-4 Small-signal equivalent circuit model at V M (transistor in G S D + - v in + - v gs + - v out g m v gs r o R + - v in + - v out g m v in r o //R saturation): v out = g m v in ( r o //R ) Then: A v = v out = g m ( r o //R ) ±− g m R v in Then: | A v ( V M ) | = g m ( V M ) R From here, get NM L and H using above formulae.
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-5 2 Dynamics C L pull-down limited by current through transistor [will study in detail with CMOS] C L pull-up limited by resistor ( t PLH RC L ) pull-up slowest V IN : LO HI V IN : HI LO V OUT : HI LO V OUT : LO HI V DD C L R V DD C L R pull-down pull-up
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-6 2 Inverter design issues: noise margins ↑⇒| A v |↑⇒ R
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lecture13annotat - 6.012 - Microelectronic Devices and...

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