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lecture14annotat - 6.012 - Microelectronic Devices and...

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS October 27, 2005 Contents : 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter: noise margins 3. CMOS inverter: propagation delay 4. CMOS inverter: dynamic power Reading assignment: Howe and Sodini, Ch. 5, § 5.4 Announcements: Cadence tutorial by Kerwin Johnson in place of reg- ular recitations on Friday 10/28
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 14-2 Key questions How does CMOS work? What is special about CMOS as a logic technology? What are the key design parameters of a CMOS in- verter? How can one estimate the propagation delay of a CMOS inverter? Does CMOS burn any power?
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 14-3 1. Complementary MOS (CMOS) Inverter Circuit schematic: V DD V IN V OUT C L Basic operation: V IN =0 V OU T = V DD V GSn <V Tn NMOS OFF NMOS OFF V SGp = V > V Tp PMOS ON V = V V T V = V >V NMOS ON V < V PMOS OFF PMOS OFF
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 14-4 Output characteristics of both transistors: I Dn 0 V SDp -I Dp V SGp V SGp =-V Tp 0 0 V DSn V GSn V GSn =V Tn 0 Note: V IN = V GSn = V DD V SGp V = V V V OU T = V DSn = V V SDp V = V V T I Dn = I Dp Combine into single diagram of I D vs. V T with V as parameter.
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V ail-to-rail” lo lo levels are 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 14-5 V DD I D V IN V OUT V DD -V IN V IN C L 0 0 V OUT ± no current while idling in any logic state Transfer function: NMOS cutoff V OUT 0 V DD PMOS triode NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation NMOS triode PMOS cutoff 0 V Tn V DD +V Tp V DD V IN ± ”r gic: gic 0 and DD ”rail-to-rail” logic: logic levels are ± high | A v | around logic threshold good noise margins
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 14-6 Transfer characteristics of CMOS inverter in WebLab:
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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 14-7 2. CMOS inverter: noise margins V OUT V DD V M 0 A v ( V M ) NM L 0 V IL V M V IH V DD V IN NM H Calculate V M Calculate A v ( V M ) Calculate NM L and H 2 Calculate V M ( V M = V IN = V OU T ) At V M both transistors saturated: 1 W n I Dn = µ n C ox ( V M V Tn ) 2 2 L n 1 W p I Dp =
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This note was uploaded on 07/20/2009 for the course ELECTRICAL 6.012 taught by Professor Prof.jesúsdelalamo during the Fall '05 term at MIT.

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lecture14annotat - 6.012 - Microelectronic Devices and...

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