{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

00_exam2spring

# 00_exam2spring - Page 1 of 9 YOUR NAME Department of...

This preview shows pages 1–3. Sign up to view the full content.

Page 1 of 9 YOUR NAME________________________________ Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Notes: 1. Unless otherwise indicated, assume room temperature and that kT/q is 0.025 V. You may also approximate [(kT/q) ln 10] as 0.06 V. 2. Open book: 6.012 text and up to one shopping cart full of notes permitted. 3. All of your answers and any relevant work must appear on these pages. Any additional paper you hand in will not be graded. 4. Make reasonable approximations and assumptions. State and justify any such assumptions and approximations you do make. 5. Be careful to include the correct units with your answers when appropriate. 6. Be certain that you have all nine (9) pages of this exam booklet and make certain that you write your name at the top of this page in the space provided. 6.012 Staff Use Only PROBLEM 1 (out of a possible 40) PROBLEM 2 (out of a possible 30) PROBLEM 3 (out of a possible 30) TOTAL

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Page 2 of 9 Problem 1 - (40 points) For Parts a, b, and c, you are given an MOS capacitor made on uniformly doped silicon and you are told that its flat-band voltage, V FB , is + 1 V, and that its threshold voltage, V T , is + 3 V. You are also told that the thickness, t ox , of the gate insulator is 80 nm (8 x 10 -6 cm) with a dielectric constant, e ox , of 3.2 x 10 -13 coul/V-cm. a) What is the doping type of the silicon, n-type or p-type? Explain your answer. n-type p-type indeterminate, because b) What is the condition of the oxide-silicon interface when v GB , the voltage on gate realtive to the silicon, is zero volts? Explain your answer. inverted depleted accumulated, because c) For what range of v GB is the silicon surface depleted? < v GB < For parts d, e, f, and g, you have an n-channel silicon MOSFET and a p-channel silicon MOSFET which have the same value of K-factor in their large signal models [where the K-factor is defined as (W/L)µ( e ox /t ox )]. The transistors are identical in all dimensions and doping level magnitudes except that the gate length, L, of one of the devices is twice that of the other. The a -factor for each device is one. d) Which transistor, if either, would you expect to be the one with the longer gate length, and why? n-channel p-channel neither, because e) What is the ratio of the electron to hole mobility in these transistors (i.e., what is the ratio of the mobility of the electrons in the channel of the n-channel MOSFET to that of the holes in the channel of the p-channel MOSFET)? Explain your answer.
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}