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00_exam2spring - Page 1 of 9 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012

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Unformatted text preview: Page 1 of 9 YOUR NAME________________________________ Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Notes: 1. Unless otherwise indicated, assume room temperature and that kT/q is 0.025 V. You may also approximate [(kT/q) ln 10] as 0.06 V. 2. Open book: 6.012 text and up to one shopping cart full of notes permitted. 3. All of your answers and any relevant work must appear on these pages. Any additional paper you hand in will not be graded. 4. Make reasonable approximations and assumptions. State and justify any such assumptions and approximations you do make. 5. Be careful to include the correct units with your answers when appropriate. 6. Be certain that you have all nine (9) pages of this exam booklet and make certain that you write your name at the top of this page in the space provided. 6.012 Staff Use Only PROBLEM 1 PROBLEM 2 PROBLEM 3 TOTAL (out of a possible 40) (out of a possible 30) (out of a possible 30) Problem 1 - (40 points) Page 2 of 9 For Parts a, b, and c, you are given an MOS capacitor made on uniformly doped silicon and you are told that its flat-band voltage, VFB, is + 1 V, and that its threshold voltage, V T, is + 3 V. You are also told that the thickness, tox , of the gate insulator is 80 nm (8 x 10-6 cm) with a dielectric constant, eox , of 3.2 x 10-13 coul/V-cm. a) What is the doping type of the silicon, n-type or p-type? Explain your answer. n-type p-type indeterminate, because b) What is the condition of the oxide-silicon interface when vGB, the voltage on gate realtive to the silicon, is zero volts? Explain your answer. inverted depleted accumulated, c) For what range of vGB is the silicon surface depleted? because < vGB < For parts d, e, f, and g, you have an n-channel silicon MOSFET and a p-channel silicon MOSFET which have the same value of K-factor in their large signal models [where the K-factor is defined as (W/L)(eox /tox )]. The transistors are identical in all dimensions and doping level magnitudes except that the gate length, L, of one of the devices is twice that of the other. The a-factor for each device is one. d) Which transistor, if either, would you expect to be the one with the longer gate length, and why? n-channel p-channel neither, because e) What is the ratio of the electron to hole mobility in these transistors (i.e., what is the ratio of the mobility of the electrons in the channel of the n-channel MOSFET to that of the holes in the channel of the p-channel MOSFET)? Explain your answer. Ratio = ______ because Problem 1 continues on the next page Page 3 of 9 Problem 1 continued f) i) Which transistor, if either, has the larger small-signal gate-to-source capacitance in saturation, Cgs? Explain your answer. n-channel p-channel they are similar, because ii) Which transistor, if either, has the larger small-signal gate-to-drain capacitance in saturation, Cgd? Include parasitic effects. Explain your answer. n-channel p-channel they are similar, because g) i) Which transistor, if either, has the larger Early effect, where by a larger Early effect we mean a greater slope in the output characteristics, i.e., in iD vs vDS? Explain your answer. n-channel p-channel they are similar, because ii) If Transistor A has a larger Early effect, as defined immediately above, than Transistor B, for which transistor is the magnitude of the Early voltage, VA, largest? Transistor A Transistor B the VA`s are similar, because For parts h, i, and j, you again have an n-channel silicon MOSFET and a pchannel silicon MOSFET which have the same value of K-factor in their large signal models. Again the transistors are identical in all dimensions and doping level magnitudes except that now the gate width, W, of one of the devices is twice that of the other. h) Which transistor, if either, would you expect to be the one with the larger gate width, and why? n-channel p-channel indeterminate, because Problem 1 continues on the next page Page 4 of 9 Problem 1 continued i) These two transistors are biased in saturation with the same magnitude of quiescent (i.e., bias) drain current, |ID|. Which device, if any, has the larger transconductance, g m, for small signal operation about this bias point? Explain your answer. n-channel p-channel they are similar, because j) These two transistors are again biased in saturation with the same magnitude of quiescent (i.e., bias) drain current, |ID|. Which device, if any, has the larger output conductance, go, for small signal operation about this bias point? Explain your answer. n-channel p-channel they are similar, because End of Problem 1 Page 5 of 9 Problem 2 (30 points) The circuit below contains an n-channel, enhancement mode MOSFET and an MOS capacitor. The MOSFET has a threshold voltage of 1 V, a K-factor of 0.1 mA/V2 , and an a-factor of one. The MOS capacitor is fabricated on the same silicon wafer as the MOSFET and with the same gate oxide as used in the MOSFET gate. The thickness of the gate oxide is 30 nm (3 x 10-6 cm) and its dielectric constant is 3.2 x 10-13 coul/V-cm. The capacitor area is 100 m by 100 m (10-4 cm-2). The voltages vA, vB, and v C are measured relative to ground. B n-channel MOSFET A + vB C + vA vC + - MOS Capacitor a) i) A voltage vC is applied sufficient to place the silicon in the MOS capacitor in accumulation at the oxide-semiconductor interface. What value of small signal capactitance, dq/dv, would you measure for this capacitor? C = ii) If the voltage vC is changed so that the semiconductor of the MOS capacitor is depleted at the oxide-semiconductor interface, is the capacitance you would measure larger or smaller than it was in (i)? Larger Smaller Similar, because b) Now suppose vC is 3 Volts, i.e., (VT + 2 Volts). i) Is the surface of the silicon at the oxide-semiconductor interface in the MOS capacitor accumulated, depleted, or inverted? Accumulated Depleted Inverted, ii) because What type of carriers comprise the mobile charge at this interface? Electrons Holes None, because Problem 2 continues on the next page Page 6 of 9 Problem 2 continued iii) How much mobile charge is there at this interface? Total mobile charge at oxide-semiconductor interface: iv) Is the magnitude of the total charge on the metal electrode of the MOS capacitor greater than, less than, or equal to the magnitude of the charge you found in (iii)? Explain your answer. Greater than Less than Equal to, because c) Suppose that for t < 0, the capacitor in the circuit pictured on the preceeding page is discharged, and that vA, v B, and vC are all zero. At t = 0, constant voltages V A and VB are applied to the terminals A and B, and VA and V B are chosen so that the MOSFET will be turned on and the capacitor will charge up to a voltage, VC, of 3 Volts. i) What are the minimum values that VA and VB can have for this to happen, i.e., for VC to reach 3 V? VA VB ii) Write the nonlinear first order differential equation one would have to solve to calculate vC(t) for t > 0. For simplicity, assume that the capacitance of the MOS capacitor is a constant, CL (this is an approximation). Assume also that VA = VB = 5 V. End of Problem 2 Page 7 of 9 Problem 3 (30 points) A bipolar transistor manufacturer who is both impressed by CMOS inverters and fearful of the threat they pose to his business, has developed a complementary bipolar logic family he calls CBL. The basic CBL inverter stage is illustrated below. The uppermost transistor is a pnp BJT and the lower transistor is an npn BJT. The transistors are designed to be symmetrical and to have the same saturation currents and alphas; thus for both IES = ICS = 10 -14 A and a F = a R = 0.9. You may use |VBE,ON| 0.6 V and |VCE,SAT| 0.2 V when appropriate. V+ pnp RB + vIN npn + vOUT - a) Check to see if the stage illustrated above actually functions as an inverter. Determine the state of each transistor with low and high inputs as directed below and indicate whether or not this stage is an inverter. i) What is the state of each transistor with vIN = V+, where V+ = 1V, and is vOUT low or high, and what is its approximate value? pnp: npn: vOUT: ii) Cutoff Active Saturated, Cutoff Active Saturated, because because because High Low, with value _________ Repeat part (i) with vIN = 0 V. pnp: npn: vOUT: Cutoff Active Saturated, Cutoff Active Saturated, because because because High Low, with value _________ Problem 3 continues on the next page Page 8 of 9 Problem 3 continued iii) Does this stage function properly as an inverter? Explain your answer Yes No, because b) On the string of inverters below indicate with arrows all of the current paths by which current flows from the power supply to ground when the input on the left is high. (It may help you to label which transistors are on and which are off, and which outputs and inputs are high and low on the figure.) V+ RB + vIN = High - RB RB c) i) Use the Ebers-Moll model to determine the values of the base current, IB, base-collector voltage, VBC, and collector-emitter voltage, VCE, of an npn transistor like the ones used in CBL when a voltage of 0.6V is applied between its base and emitter and the collector current equals the base current, i.e., iC = iB, as shown below: IC=IB IB=? + + VBE VCE = ? =0.6 V - 2 I B IB = VBC = VCE = Problem 3 continues on the next page. Problem 3 continued Page 9 of 9 ii) In the space below explain briefly (25 words or less) the relevance of your calculation above to the inverter chain in Part b. d) Next we want to consider the impact of fan-out on the low and high output voltage levels of CBL inverter stages. Consider a CBL inverter whose output is taken to two stages, i.e. a stage with a fan-out of two (2), as illustrated below. V+ RB + vIN + vOUT - RB RB Stage with a fan-out of two (2) With a fan-out of two (2) is the low output value (i.e., vOUT with vIN high) higher or lower than it is with a fan-out of one (1)? Low output value: Lower Higher No different, because (e) Finally, in the space provided below, briefly explain (25 words or less) why we never worried about the impact of fan-out on the voltage levels of CMOS inverters. End of Problem 3 End of Exam ...
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This note was uploaded on 07/20/2009 for the course CSAIL 6.012 taught by Professor Prof.cliftonfonstadjr. during the Fall '03 term at MIT.

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