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Unformatted text preview: Page 1 of 10 YOUR NAME________________________________ Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits
Exam No. 2 Notes: 1. Unless otherwise indicated, assume room temperature and that kT/q is 0.025 V. You may also approximate [(kT/q) ln 10] as 0.06 V. 2. Open book: 6.012 text and up to 10 lb. of notes permitted. 3. All of your answers and any relevant work must appear on these pages. Any additional paper you hand in will not be graded. 4. Make reasonable approximations and assumptions. State and justify any such assumptions and approximations you do make. 5. Be careful to include the correct units with your answers when appropriate. 6. Be certain that you have all ten (10) pages of this exam booklet, and make certain that you write your name at the top of this page and pages 2, 5, and 8 in the spaces provided. 7. The exam is long, but has numerous small parts, many of which are independent. Most answers are worth 3 pts. (a few are worth 2 or 4 pts). Don't spend too much time on any one question; move on and come back to it later. 6.012 Staff Use Only PROBLEM 1 PROBLEM 2 PROBLEM 3 TOTAL (out of a possible 38) (out of a possible 34) (out of a possible 28) Problem 1 - (38 points) Your name Page 2 of 10 This question has three independent parts, each with several sub-parts. a) You have two npn bipolar junction transistors, BJT A and BJT B, that are identical except that BJT A has base and collector doping levels that are twice those of BJT B, i.e., NAB(BJT A) = 2 NAB(BJT B) and NDC(BJT A) = 2 NDC(BJT B). i) Which BJT has the larger Early voltage, and why? O BJT A O BJT B O Neither because ii) Which BJT has the larger forward alpha, a F, (and bF, too), and why? O BJT A O BJT B O Neither because iii) Which BJT, when biased in its FAR with VCE = 4 V, has the larger Cm, and why? O BJT A O BJT B O Neither because iv) Which BJT, when biased in its FAR with IC = 1 mA, has the larger gm, and why? O BJT A O BJT B O Neither because V DD A B C b) Consider the two-input CMOS logic gate above at right. i) When both inputs are low, what is the output, C? O High O Low O Can't say, because Problem 1 continues on the next page Problem 1 continued ii) When input A is high and input B is low, what is the output, C? O High O Low O Can't say, because Page 3 of 10 iii) Compare the time it takes the output to switch from high to low (discharging cycle) when both inputs are abruptly changed from low to high, with the time it takes when only one input is abruptly changed from low to high? Is it faster, slower, or similar? Explain. O Faster O Slower O Similar because iv) When both inputs are low and the both p-channel MOSFETs are "on" they behave together like a transistor with a gate length, L, that is the sum of the gate lenghts of the individual transistors, i.e., 2 Lmin in this case. How wide should the p-channel MOSFETs be in terms of W n, the width of the n-channel MOSFETs, to make the lowto-high output switching time (charging cycle) of this gate as least as fast as the slowest high-to-low output switching. Assume m e = 2 mh. Width: ___________ c) _______ Consider the current mirror on the right below. Both transistors have vBE,ON = 0.6 V, vCE,SAT = 0.2 V, and bF = 100, but the transistor on the right has twice the area as the one on the left (they are otherwise identical). You may neglect the base currents in the first three sub-parts of this question. i) What is the collector current of Q1 ? 3V 9.6 kW R Q1 Q2 IC(Q1 ) = ________________ Problem 1 continues on the next page Problem 1 continued Page 4 of 10 ii) What is the collector current of Q2 , assuming Q2 is in its FAR? Recall that the areas of Q1 and Q2 differ. IC(Q2 ) = ________________ iii) What is the range of values for R over which Q2 remains in its FAR? _________ < R < ___________ iv) What are the base currents of Q1 and Q2 ? IB(Q1 ) = ________________ IB(Q2 ) = ________________ End of Problem 1 Problem 2 (34 points) Your name Page 5 of 10
A G S D iD + (S) p+ p+
(G) (B) (D) vAB n-Si - B B This problem concerns the p-channel MOSFET illustrated on the left above. You are told that the drain current of this MOSFET can be written as -1000(vGS - V T)2 A, when vDS < vGS - VT < 0, but your are not told VT. You are told, however, that when its gate and drain are connected together, and its source and substrate are also connected together, as is shown above on the right, the current-voltage characteristic of this "diode" looks like that shown below: iD 1 mA -0.6 V 1V vAB -1 mA a) What is the threshold voltage, VT, of this MOSFET? VT = ________________ Volts Problem 2 continues on the next page Page 6 of 10 Problem 2 continued b) On the small device cross-sections below indicate the primary current path through the structure when vAB < 0 V (on the left), and when vAB > 1 V (on the right)
A B A B p+ p+ p+ p+ n-Si n-Si . i) Current path when vAB < 0 V ii) Current path when vAB > 1 V c) Write an expression for i D as a function of vAB in each of the three ranges defined below: i) Range I: vAB < 0 V iD = __________________________ ii) Range II: 0 V < vAB < 1 V iD = __________________________ iii) Range III: 1 V < vAB iD = __________________________ d) In the space at right draw a quasi-static one-element linear equivalent circuit model for this "diode". By "quasi-static" we mean that you can ignore charge stores and base your linear equivalent circuit on only the static current-voltage model. e) Determine the value of the element in your linear equivalent circuit at each of the following three bias points: i) iD = + 1 mA Value: ________________ Problem 2 continues on the next page Page 7 of 10 Problem 2 continued ii) vAB = + 0.5 V Value: ________________ iii) iD = -1 mA, vAB = -0.6 V Value: ________________ f) Draw on the axes below the characteristics of this two-terminal "device" when a 1 V voltage source is inserted between the substrate contact and the source contact as indicated in the figure to the right. The dashed line on the axes is the earlier curve of the characteristics when the source and back contact are shorted.
A B p+ p+ n-Si - +
iD 1V 1 mA -0.6 V 1V vAB -1 mA End of Problem 2 Your name Problem 3 - (28 points) Page 8 of 10 Cross-section A-A' G
0 -0.01 xD p-Si B
x (m) (20 + xD)/2 20 S
n+ G A p-Si B 100 m 20 m A' This question concerns the MOS capacitor structure above. This device was fabricated using state-of-the-art technology on p-type Silicon, N A = 1017 cm-3, and has a gate oxide 10 nm thick. The dielectric constant of the gate oxide is 3 x 10-11 F/cm, and the electrostatic potential of the gate metal, fm, is 0.35 V relative to intrinsic Si. In the lower figure, xD is the edge of the depletion region under the gate. a) What is the flat-band voltage, VFB, of this structue? VFB = ____________________ b) When vBS = 0, what is the electrostatic potential drop, Df, in the silicon at threshold, i.e. when v GS = VT? Df in Si (vGS = VT, VBS = 0) = ____________________ Problem 3 continues on the next page Problem 3 continued c) Page 9 of 10 Now consider what would happen if VBS was -2 V. i) What would the electrostatic potential drop, Df, in the silicon be now at vGS = VT? Df in Si (vGS = VT, VBS = -2V) = ____________________ ii) Is |VT| larger or smaller now, i.e., when VBS is -2 V instead of 0 V? Explain O Larger O Smaller O Similar because d) The "diode" between the n-type channel and the p-type Si will act like a photodiode if it is illuminated. For example, suppose that this structure is illuminated with light that generates M hole-electron pairs per square centimeter per second in the plane under the gate half-way between the edge of the depletion region, xD, and the back, i.e., at x = (20 + xD)/2 m. Assume that the minority carrier diffusion length is much greater than 10 m, that M is 6 x 1018 pairs/cm2 -s, and that the size of the illuminated area under the gate is 100 m by 100 m (10-2 cm by 10 -2 cm). Ignore any lateral diffusion of carriers, i.e., they only diffuse in the x-direction. Finally, set vBS = 0 as it was in Part b. The boundary conditions are then as follows: When it is in the flat-band condition (vGS = V FB) the surface of silicon under that gate behaves like a reflecting boundary. When vGS > VT, the inversion layer of electrons that is formed (i.e., the channel) acts like the n+-side of a p-n+ junction and is a sink for excess electrons in the p-type Si. The back contact at x = 20 m is an ohmic contact. i) On the axes below sketch the minority carrier density, n'(x), in this device when vGS = V FB. Assume low-level injection conditions pertain and that n' at x = (20+xD)/2 m is the value indicated on the figure.
n', p' n' @ x = (20 + xD)/2 x (m) -0.01 0 xD (20 + xD)/2 20 ii) What is the short circuit current between the contacts S and B under the conditions of part (i), i.e. when vGS = VFB? I = __________________ Problem 3e continues on the next page Problem 3e continued Page 10 of 10 iii) On the axes below sketch the minority carrier density in this device when vGS > VT. Assume low-level injection conditions pertain and that n' at x = (20+xD)/2 m is the value indicated on the figure.
n', p' n' @ x = (20 + xD)/2 x (m) -0.01 0 xD (20 + xD)/2 20 iv) What is the short circuit current between the contacts S and B under the conditions of part (iii), i.e. when v GS > V T? You may assume xD << 20 m if you feel you need to know xD. I = __________________ End of Problem 3; End of Exam ...
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This note was uploaded on 07/20/2009 for the course CSAIL 6.012 taught by Professor Prof.cliftonfonstadjr. during the Fall '03 term at MIT.
- Fall '03