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Unformatted text preview: Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits
FINAL EXAMINATION
Open Book. Notes: 1. Unless otherwise indicated, assume room temperature and that kT/q is 0.025 V, kT/q ln 10 = 60 mV, and ni = 1010 cm3 for Si. Use q = 1.6 x 1019 Coul. 2. This test is designed so that most parts can be worked independently of the others. 3. All of your answers and any relevant work must appear on these pages. Any additional paper you hand in will not be graded. 4. Make reasonable approximations and assumptions. State and justify any such assumptions and approximations. 5. Be certain that you have all twelve (12) pages of this exam booklet and make certain that you write your name at the top of this page as indicated. 6. You may see your final exam in Room 133058 beginning January 7, 2002. Grader Use Only PROBLEM 1 PROBLEM 2 PROBLEM 3 PROBLEM 4 TOTAL (out of 30 possible) (out of 25 possible) (out of 20 possible) (out of 25 possible) Problem 1  (30 points) Three independent miniproblems Page 2 of 12 a) An isolated ntype Si sample with 101 7 cm3 donors, and having an electron mobility of 1600 cm2 /Vs, hole mobility of 600 cm2 /Vs, and minority carrier lifetime of 105 s, is illuminated with light generating GL holeelectron pair/cm3 s uniformly throughout its bulk, and leading to an excess hole population of 101 8 cm3. i) What are the thermal equilibrium carrier concentrations, no and po, in this sample at room temperature? no = po = ii) What is the conductivity, s, of the illuminated sample? s= iii) How (approximately) are n' and p' related to GL? Explain n',p' GL1/2 n',p' GL n',p' GL2 , because b) This miniproblem concerns the MOS capacitor structure illustrated below. In this structure the n+Si plays the role of the metal gate. The oxide thickness is 50 nm (5 x 106 cm) and its dielectric constant is 3.3 x 1013 F/cm. The dielectric constant of Si is 1012 F/cm and ni = 101 0 cm3 at room temperature. G n+ Si 1019 cm 3 0 t ox pSi 1017 cm 3 B x i) What is the flatband voltage, VFB, of this structure? VFB = Problem 1 continues on the next page. Problem 1 continued ii) Page 3 of 12 At threshold (that is, when the surface of the pSi at x = 0 is at the threshold of inversion), what is the change in electrostatic potential, Df, crossing the depletion region in the ptype Si and how wide is this depletion region? Df = xDp = iii) What is the width of the depletion region and what is the potential change in the n+Si under the same conditions as in Part (ii)? xDn+ (in n+Si) = Df (in n+Si) = c) Consider the passive circuit shown below. In the midband range this circuit functions as a voltage divider. 20 mF va +  1 kW 0.5 kW 1 pF 30 pF 1.5 kW vout 1 kW i) What is the midband voltage gain, Av = vout/va , of this circuit? Av = ii) What is wLO for this circuit? wLO = iii) Estimate wHI for this circuit. wHI = End of Problem 1 Page 4 of 12 Problem 2 (25 points) In an integrated circuit, when a designer needs a diode it is easiest to use a transistor and connect it so it functions as a diode. A transistor, after all, contains two pn junctions. There are at least five ways to connect an npn transistor as a diode; three of them are pictured below: A + iD A + iD A + iD vAB
(a) B vAB
(b) B vAB
(c) B For purposes of this question, assume that the npn bipolar junction transistor in question has a base doping that is 4 times the collector doping and 1/4 the emitter doping, that base width is the same as the emitter width and 1/2 the collector width, and that the electron mobility is twice the hole mobility; that is: NDE = 4 NA B = 16 NDC, wE = wB , wC = 2wB , and e = 2h a) i) Which of these diode connections will have the largest small signal depletion capacitance at a reverse bias of 1 V, and why? Check all that apply. a( ) b( ) c( ) All are similar ( ) because: ii) Which of the three diode connections will have the largest small signal conductance about the bias point ID = 1 mA, and why? Check all that apply. a( ) b( ) c( ) All are similar ( ) because: Problem 2 continues on the next page Problem 2 continued Page 5 of 12 b) i) On the axes provided below sketch the excess carrier populations as a function of position in the emitter and collector, respectively, of connections a, b, and c, when a forward bias, VA B, of 0.6V is applied to the diode. The profile in the base of Connection a is indicated on the axes; use the same scale in all plots.
Connection a: p',n' x w E Connection b: p',n' wB wB +w C x w E Connection c: p',n' wB wB +w C x w E wB wB +w C ii) Which one of the three diode connections a, b, or c will have the smallest small signal diffusion capacitance at a forward bias of 0.6 V, and why? a() b( ) c( ) All are similar ( ) because: Problem 2 continues on the next page Problem 2 continued c) Page 6 of 12 Use the EbersMoll Model for the large signal characteristics of a bipolar junction transistor (pictured below) to show that iD vs vA B of Connection c can be written as iD = ID S (exp qvA B/kT  1) and find an expression for ID S of Connection c in terms of the EbersMoll Model parameters. C + vBC
+ B + aFiF IES iF ICS iR aRiR E vCE vBE ID S = End of Problem 2 Problem 3  (20 points) Page 7 of 12 A SATFET is a field effect transistor having three terminals (gate, source, and drain) and represented by the symbol below; it can be either n or pchannel. A nchannel: G iG + vGS iD D + vDS pchannel: vSG G iG + S + vSD  S iD D SATFET is similar to a MOSFET but has somewhat different terminal characteristics. The static terminal characteristics of n and p channel SATFETs are as follows: nchannel iG = 0 under all conditions 0 if vGS < VT iD = A (vGS  VT) vDS (1 + lvDS) if vGS > VT and 0 < vDS < VSat B (vGS  VT) (1 + lvDS) if vGS > VT and vDS > VSat pchannel iG = 0 under all conditions 0 if vSG < VT  iD = A (vSG  VT) vSD (1 + lvSD) if vSG > VT and 0 < vSD < VSat B (vSG  VT) (1 + lvSD) if vSG > VT and vSD > VSat with VT = 0.25 V, VSat = 0.5 V, l = 0.01 V1, A = 2 x 103 A/V2 , B = 103 A/V. The output characteristics (i.e., iD vs vDS) for an nchannel SATFET are shown below for the range 0 < vDS < 2 V, for vGS = 0, 0.5, 0.75, and 1.0 V. Note that l has been approximated as being zero for purposes of this sketch. iD (mA)
1.0 vDS (V)
1.0 2.0 a) Indicate on the characteristics what region corresponds to the "forward active region", i.e., what would be the preferred bias region when using this device in linear amplifier applications. Problem 3 continues on the next page Problem 3 continued Page 8 of 12 b) i) In the space to the left below draw a complementary SATFET inverter stage that would be the analog of a CMOS inverter. vOUT (V)
2.0 1.0 vIN (V)
1.0 2.0
ii) On the axes provided above to the right plot the transfer characteristic of the SATFET inverter you drew above on the left. Assume that the power supply voltage is 2 V, and approximate l as zero (for this part only). c) A possible incremental linear equivalent circuit for this device is shown below. Find expressions for gi, gm, and go valid for bias points for which VGS > VT and VDS > VSat. Give your expressions in terms of the approximate quiescent currents. g vgs s
i) Input conductance, gi: d gi gmvgs go vds s gi = ii) Transconductance, gm: gm = Problem 3 continues on the next page Page 9 of 12 Problem 3 continued iii) Output conductance, go: go = d) This question concerns the opencircuit midband incremental voltage gain of a SATFET, Av,oc, and how it depends on the bias current. i) Derive and expression for the smallsignal, midband opencircuit voltage gain, Avoc, of a SATFET as a function of the approximate drain current. ii) In 25 words or less compare this behavior to that of a MOSFET and a BJT. End of Problem 3 Problem 4  (25 points) Page 10 of 12 The circuit below uses three identical nchannel MOSFETs and two identical npn BJTs in a differential amplifier. Note that each side of the differential amplifier is a cascode circuit. The transistor characteristics are listed below the circuit. 5V RL = 3 kW RL = 3 kW Q1 vOUT1 vOUT2 Q2 iD3 + vIN1 Q3 vC iD4 Q4 vIN2 2 mA + V B  Q5 5V Characteristics: nchannel MOSFETs: K = 2 x 103 A/V2 , VT = 1 V, Va  = 20 V. npn BJTs: b = 100, vBE @ 0.6 V at the current of interest, Va  = 100 V. a) With both inputs zero (i.e, vIN1 = vIN2 = 0) determine the indicated quiescent currents and voltages. Specify units: i) ID3 (= ID4) ID3 = ii) VOUT1 (= VOUT2) VOUT1 = iii) VC VC = Problem 4 continues on the next page. Problem 4 continued iv) VCE1 (= VCE2) VCE1 = v) VDS3 (= VDS4) VDS3 = Page 11 of 12 b) In the spaces provided below draw two midband linear equivalent half circuits (LEHCs) for this differential amplifier, one for commonmode inputs and one for differencemode inputs. Label all of the elements in them. i) Commonmode LEHC: ii) Differencemode LEHC: c) Derive literal expressions for the commonmode and differencemode voltage gains, Avc and Avd, respectively, of this differential amplifier. Use the definitions for Avc and Avd indicated by the blanks provided for your answers. The output conductances of Q1 , Q2 , Q3 , and Q4 are of insignificant effect and should be neglected in these derivations. i) Commonmode voltage gain, Avc = voc/vic: Avc = voc/vic = Problem 4 continues on the next page Problem 4 continued ii) Differencemode voltage gain, Avd = vod/vid: Page 12 of 12 Avd = vod/vid = End of Problem 4 End of Exam Happy Holidays; have a great IAP ...
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 Fall '03
 Prof.CliftonFonstadJr.

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