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Unformatted text preview: Triode n-channel Saturation (FAR) iD K[vGS - VT(vBS) - vDS/2]vDS iDiD K[vGS -- V T(vBSBS2/2a[1 + lvDS]/2 K [v GS VT(v )] )]2 Cutoff
Clif Fonstad, 10/03 vDS
Lecture 13 - Slide 10 Large signal models: when will we use them?
Digital circuit analysis/design: This requires use of the entire circuit, and will be the topic of the two lectures after the next (15 and 16). Bias point analysis/design: This uses the FAR models (lec. 17ff). C C iI = b I C BJT iB B+ bFiB IBS IBB i C B B+
0.6 vBE V vBE E E
iID D MOSFET
+ D i D = (K/2)[vGS - V T]
2 D G+ + B vGS VGS = (2IDS
S /K)1/2 + VT vGS vBS Clif Fonstad, 10/03 S Lecture 13 - Slide 11 6.012 - Electronic Devices and Circuits Lecture 13 - Large-Signal Models - Summary Refined device models
1. Junction diodes - depletion and diffusion charge 2. BJTs - at EB junction: depletion and diffusion charge at CB junction: depletion charge (focus on FAR) 3. MOSFETs - between B and S, D: depletion charge of n+-p junctions between G and S, D, B: gate charge (the dominant store) in cut-off: Cgs Cgd 0; all is Cgb linear region: Cgs = Cgd = W L Cox*/2 in saturation region: Cgs = (2/3) W L Cox* Cgd = 0 (only parasitic overlap) The Early Effect:
1. Base-width modulation in BJTs: wB(vCE) In the F.A.R.: iC bFo(1 + lvCE)iB 2. Channel-length modulation in MOSFETs: L(vDS) In saturation: iD Ko (vGS VT)2 (1 + lvDS)/2a Extrinsic parasitics: Lead resistances, capacitances, and inductances Clif Fonstad, 10/03 Lecture 13 - Slide 12...
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This note was uploaded on 07/20/2009 for the course CSAIL 6.012 taught by Professor Prof.cliftonfonstadjr. during the Fall '03 term at MIT.
- Fall '03