lec18 - 6.012 Electronic Devices and Circuits Lecture 18...

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Unformatted text preview: 6.012 - Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements Handouts - Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 - Wednesday night, November 5, Room 10-250 Closed book; formula sheet provided; one crib sheet permitted Review - Biasing and amplifier metrics Current mirrors in emitter and source circuits Performance metrics: gains (voltage, current, power); input and output resistances; power dissipation; bandwidth Mid-band analysis Biasing capacitors: short circuits above wLO Device capacitors: open circuits below wHI Midband: wLO < w < wHI Common emitter/source Common base/gate Emitter/source follower (also called common collector/drain) Series feedback (more commonly: emitter/source degeneration) Shunt feedback Building-block stages Clif Fonstad, 11/03 Lecture 18 - Slide 1 Linear amplifier performance metrics: The characteristics of linear amplifiers that we use to compare different amplifier designs, and to judge their performance and suitability for a given application are given below: iin + vin iout Linear Amplifier + vout - Rest of circuit Voltage gain, Av = vout/vin Current gain, Ai = iout/iin Power gain, Apower = Pout/Pin = voutiout /viniin = AvAi Input resistance, rin = vin/iin itest Linear Amplifier + vtest - Clif Fonstad, 11/03 Output resistance, rout = vtest/itest with vin = 0 DC Power dissipation, PDC = (V+ - V-)(SIBIAS's) Lecture 18 - Slide 2 Linear equivalent circuits: pn diodes: gd b a Cd gd = q|ID|/kT Cd = gdtd + Cdpl(VAB) BJTs: (in FAR) b gp e g Cm Cp gmv p go + vp - c e Cgd (in saturation) gm = q|IC|/kT gp = gm/bF go = |IC/VA| [or l |IC|] Cp = gmtb + Cdpl,be(VBE) [tb = wB2/2De] Cm = Cdpl,bc(VBC) gm = K(VGS - VT) = (2K|ID|)1/2 gmb = hgm [h = {eSiqNA/2(|2fp| - VBS)}1/2/Cox*] go = |ID/VA| [or l |ID|] Cgs = (2/3) WL Cox* Cgd: G-D fringing and overlap capacitance, all parasitic Csb, Cgb, Cdb: depletion capacitances Lecture 18 - Slide 3 MOSFETs: + v gs sv bs b+ Cgs gmv gs gmb v bs Cdb d + v go ds -s Csb Cgb Clif Fonstad, 11/03 BJTs and MOSFETs biased for linear amplifier applications +V +V IBIAS +V +V IBIAS IBIAS -V -V -V IBIAS -V npn Clif Fonstad, 11/03 pnp n-MOS p-MOS Lecture 18 - Slide 4 Examples of current mirror biased BJT circuits: V+ +V V+ RREF IC Q1 RREF IC Q1 IBIAS -V Above: Concept Right: Implementations Q2 Q3 Q2 Q3 V- BJT Mirror IC (AQ3/AQ2) IREF Clif Fonstad, 11/03 MOSFET Mirror IC (KQ3/KQ2) IREF Lecture 18 - Slide 5 V- Looking at a complicated circuit: Lesson I Find the biasing circuitry and represent it symbolically Consider the following example: + 1.5 V Q1 A Q2 Q3 Q4 Q5 Q8 Q10 Q11 A Q9IBIAS5 R1 Q6 Q7 R2 + vIN2 B IBIAS2 Q23 R3 Q12 Q13 Q14 Q22 B IBIAS6 Q16 Q15 Q17 + vOUT - + vIN1 B B IBIAS1 Q19 Q20 B IBIAS3 Q21 B IBIAS4 Q24 Q18 Circuitry providing the VREF's - 1.5 V 8 of the 24 transistors are "only" used for biasing the other 16 transistors! If we get them out of the picture for awhile, the circuit looks simpler: Lecture 18 - Slide 6 Clif Fonstad, 11/03 Looking at a complicated circuit: Lesson I, cont. segregating out the biasing circuitry Indicating the current sources symbolically lets you focus on the action: + 1.5 V Q2 Q3 Q4 Q5 Q8 Q10 Q11 Q9 Q6 Q7 R2 + vIN2 IBIAS2 Q12 Q13 R3 Q14 Q15 Q17 IBIAS3 - 1.5 V IBIAS4 Q16 + vOUT IBIAS5 + vIN1 - IBIAS1 IBIAS6 Clif Fonstad, 11/03 16 transistors left. In Lessons II and III we reduce the number to 5! Stay tuned... Lecture 18 - Slide 7 Three BJT single-transistor amplifiers V+ V+ V+ + vin IBIAS CO + vout CE VCOMMON EMITTER Input: base Output: collector Common: emitter CO vout CI + vIN + + vin IBIAS V- CO + vout - IBIAS V- EMITTER FOLLOWER Input: base Output: emitter Common: collector COMMON BASE Input: emitter Output: collector Common: base + vin Lecture 18 - Slide 8 + + vin vout Clif Fonstad, 11/03 + vin - + vout - + vout - Three MOSFET single-transistor amplifiers V+ V+ V+ + vin - CO + vout IBIAS CE VCOMMON SOURCE Input: gate Output: drain Common: source Substrate: to source CO + vout CI + vIN - + vin IBIAS V- CO + vout - IBIAS V- COMMON GATE Input: source; Output: drain Common: gate; Substrate: to ground SOURCE FOLLOWER Input: gate Output: source Common: drain Substrate: to source + + vin + vout Lecture 18 - Slide 9 + + vin vout Clif Fonstad, 11/03 vin + vout - Single-transistor amplifiers with feedback V+ V+ + vin IBIAS CO + vout RF CE RF + vin - CO + vout CE V- IBIAS also termed "emitter degeneration" Series feedback + V- Shunt feedback RF + + vin vout Lecture 18 - Slide 10 + vin Clif Fonstad, 11/03 vout RF - The "mid-band"concept: frequency range of constant gain and phase V+ + vin - CO + vout IBIAS CE V- Common emitter example: The linear equivalent circuit for the common emitter amplifier stage on the left is drawn below with all of the elements included: Cm rt vt + CO + gmv p go gLOAD CE v out gnext + v in gp + vp rIBIAS Cp - The capacitors are one of two types: Biasing capacitors: typically very large (in F range) (CO, CE, etc.) effectively shorts above some w LO Device capacitors: typically very small (in pF range) (Cp, Cm, etc.) effectively open until some wHI Clif Fonstad, 11/03 Lecture 18 - Slide 11 The "mid-band"concept, cont.: At frequencies above some value ( wLO) The biasing capacitors look like shorts: Cm rt vt + CO + + v in gp + vp rIBIAS gmv p Cp CE go gLOAD v out gnext - At frequencies below some other value ( wHI) The parasitic capacitors look like open circuits: Cm rt vt + CO gmv p + go gLOAD CE Lecture 18 - Slide 12 + v in gp + vp rIBIAS Cp v out gnext Clif Fonstad, 11/03 The "mid-band"concept, cont.: If wLO < wHI, then there is a range where all of the capacitors are either short circuits (the biasing capacitors) or open circuits (the parasitics). Cm CO rt vt + + v in gp + vp rIBIAS gmv p Cp CE + go gLOAD v out gnext - We call the frequency range between wLO and wHI the "midband" range; for frequencies in this range our model is simply: + + + rt + gl gmv p v in gp vp go v out vt (= gLOAD + gnext ) Valid for wLO < w< wHI, i.e. in the "mid-band" range. Clif Fonstad, 11/03 [where all bias capacitors are shorts and all parasitic capacitors are open] Lecture 18 - Slide 13 Common emitter/source amplifiers Common emitter V+ + - vt rt + v in gp - + vp - gmv p go + v out - gl + vin - CO + vout IBIAS CE V- Mid-band LEC for common emitter gl : conductance of "LOAD" and anything connected at "vout" Av: Ai: Rin: Rout: BJT -gm/(go + gl) -gm(Ro||rl) -b gl/(go + gl) @ -b rp 1/go = ro MOSFET -gm/(go + gl) -gm(Ro||rl) 1/go = ro A good workhorse gain stage Clif Fonstad, 11/03 Lecture 18 - Slide 14 go Common base/gate amplifiers rt V + Common gate CO + vt - + Clif Fonstad, 11/03 vout CI BJT MOSFET + vIN IBIAS Av: (gm+go)/(gl+go) (gm+gmb+go)/(gl+go) @ gm(rl||ro) @ (gm+gmb)(rl||ro) VAi: (gm+go)/(gm+go+gp+gpgo/gl) 1 @1 Rin: [gm+gp+go(gl-gm)/(gl+go)]-1 [gm+gmb+go(gl-gm-gmb)/(gl+go)]-1 @ 1/(gm+gp) = rp/(b+1) @ 1/(gm+gmb) Rout: ro[1 + (gm+go)/(gp+gt)] ro[1 + (gm+gmb+go)/gt] @ (b+1)ro A very low Rin, large Rout stage often used to complement other stages Lecture 18 - Slide 15 gl : conductance of "LOAD" and anything connected at "vout" The conductance of IBIAS can be neglected. Mid-band LEC for common gate + + (gm + gmb )v sg v in v out = v sg - gl Emitter/source followers V+ Emitter Follower rt vt + + v in gp + vp - gmv p + gl v out go + vin IBIAS V- CO + vout Av: Ai: - - Mid-band LEC for emitter follower gl : conductance of "IBIAS" and anything connected at "vout" BJT 1/[1 + (go+gl)/(gm+gp)] @1 b gl/(go+gl) 1/gp + (b+1)/(go+gl) = rp + (b+1) ro||rl MOSFET 1/[1 + (go+gl)/gm] @1 [go+gl+gm]-1 @ 1/gm Lecture 18 - Slide 16 A great output buffer stage with small Rout, big Rin Clif Fonstad, 11/03 Rin: Rout: [go+gl+(gm+gp)/(1 + gprt)]-1 @ (rt + rp)/(b+1) Series Feedback: emitter/source degeneration Emitter degeneration rt V+ + v in gp vt - + + vp RF gmv p + go v out gl + vin IBIAS CO + vout RF CE V- Mid-band LEC emitter degeneration gl : conductance of "LOAD" and anything connected at "vout" Av: Ai: Rin: Rout: BJT @ -rl/RF @b @ rp + (b+1)RF @ 1/go MOSFET @ -rl/RF @ 1/go Useful in discrete device circuit design; we use to understand common-mode gain suppression in differential amplifiers Clif Fonstad, 11/03 Lecture 18 - Slide 17 Feedback: shunt feedback element rt RF Shunt + + feedback V + + v in gp v p vt RF + vin IBIAS CE VRout: gmv p go + v out - gl Mid-band LEC for a shunted common-emitter CO + vout - gl : conductance of "LOAD" and anything connected at "vout" Av: Ai: Rin: BJT -(gm-GF)/(go+GF) @ -gmRF @ - gl/GF 1/[gp +GF(1-Av)] @ rp||RF/(1-Av) @ (ro||RF) MOSFET -(gm-GF)/(go+GF) @ -gmRF @ - gl/GF RF/(1-Av) @ (ro||RF) Used to stabilize high gain circuits and in transimpedance amplifiers; the same topology leads to the Miller effect (Lec. 24). Clif Fonstad, 11/03 Lecture 18 - Slide 18 Summary of the stages (bipolar) Voltage Current gain, Av gain, Ai gm b gl Common emitter (= -gm rl ') [ go + gl ] [ go + gl ] gm Common base 1 (= gm rl ') [go + gl ] gl [ gm + gp ] Emitter follower 1 b b [ gm + gp + go + gl ] [ go + gl ] Emitter degeneration r - l b (series feedback) RF g [ g - GF ] -g R Shunt feedback - m - l m F GF [ go + G F ] Input resistance, R i rp rp [b + 1] Output resistance, R o 1^ ro = ~ go [b + 1] ro rt + rp [b + 1] ro ^ 1 ro RF = ~ go + GF ] [ rp + [b + 1] rl ' rp + [b + 1] RF 1 gp + GF [1- Av ] Clif Fonstad, 11/03 Lecture 18 - Slide 19 6.012 - Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Summary Mid-band analysis Biasing capacitors: typically in mF range should/can be avoided completely in modern IC design (wLO = 0) Device capacitors: typically in pF range; goal is to make as small as possible Midband: no capacitors in incremental analysis; gain and phase constant want as wide as possible (we won't find wLO and wHI until Lec. 22) Building-block stages Common emitter/source: good voltage and current gain large Rin and Rout good gain stage Common base/gate: very small Rin; very large Rout unity current gain; good voltage gain will find paired with other stages to form "cascode" unity voltage gain; good current gain an excellent output stage or buffer Emitter/source follower: very small Rout; very large Rin Series feedback: moderate voltage gain dependant on ratio of resistors Shunt feedback: used in transimpedance amplifiers Clif Fonstad, 11/03 Lecture 18 - Slide 20 ...
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