lec21 - 6.012 - Electronic Devices and Circuits Lecture 21...

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6.012 - Electronic Devices and Circuits Lecture 21 - Linear Amp. Analysis and Design II - Outline Announcements Handouts - Lecture Outline and Summary Design Problem - Answer sheet and final specs out Wed. Review - Non-linear and active loads Non-linear loads: large r eff @ large I, small V (Use biased BJT or MOSFET) Active loads: current mirror, Lee load (Reduced common-mode gain) Expressing gain in terms of device parameters and constraints General Multi-stage Amplifiers - using design problem as example Gain and bias analysis Input and output voltage swings Output stages: output resistance, loading on gain stage Specialty stages Emitter-/source-coupled pairs (diff amps) Push-pull or Totem pole output Cascode Darlington Clif Fonstad, 11/03 Lecture 21 - Slide 1
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Current Source Loads: a higher maximum gain - current source loads eliminate the compromise between voltage gain and output voltage swing V + I LOAD C O + v out + - v in - I BIAS C E Maximum Voltage gain V - g m qI C kT V A , eff Bipolar : A = = = g v ,max oL + g oQ I C V AL + I C V AQ V thermal g m 2 I D [ V GS V T ] 2 V A , eff MOSFET* : A = = g v ,max oL + g oQ I D V AL + I D V AQ [ V GS V T ] min V AL V AQ with V A , eff [ V AL + V AQ ] Typically V A,eff >> [I R L ] max Clif Fonstad, 11/03 Lecture 21 - Slide 2
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Bipolar MOSFET Linear resistor Current source Active load, A v,diff Active load, A v,com Achieving the maximum gain: Comparing linear resistors, current sources, and active loads MAXIMUM GAIN Bipolar MOSFET [ I C R L ] [ I D R L ] V Linear resistor loads max max thermal [ V GS V T ] min 2 V A , eff 2 V A , eff Current source loads V thermal [ V GS V T ] min V A , eff V A , eff V Difference mode µ µ thermal [ V GS V T ] min Active loads Common mode µ V thermal µ [ V GS V T ] min V A , bias V A , bias Observations: - Non-linear (current source) loads typically yield higher gain than linear resistors, i.e. V A,eff >> [I D R L ] max - Bias level is not important to BJT stage gain - A MOSFET should be biased at low level for high gain - For active loads what increases A vd , decreases A vc Clif Fonstad, 11/03 Lecture 21 - Slide 3
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6.012 - Electronic Devices and Circuits Fall 2003 Design Problem Circuit Full schematic Q 1 A B Q 18 R 1 Q 5 Q 4 Q 3 Q 2 Q 9 v IN2 + 1.5 V - 1.5 V B v IN1 + - Q 6 + - Q 7 Q 19 B Q 12 Q 13 Q 21 B B Q 11 Q 10 Q 8 Q 20 Q 22 Q 24 Q 15 Q 16 Q 17 v OUT + - B A Q 14 Q 23 R 2 R 3 Source- Emitter- Push-pull Bias chain Common-source follower Common-source follower output gain stage with stage with gain stage with Lee load
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This note was uploaded on 07/20/2009 for the course CSAIL 6.012 taught by Professor Prof.cliftonfonstadjr. during the Fall '03 term at MIT.

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lec21 - 6.012 - Electronic Devices and Circuits Lecture 21...

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