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6.012  Electronic Devices and Circuits, Fall 2003
CMOS Gate Delays, Power, and Scaling
GATE DELAYS
Earlier in the term (Lec. 16) we calculated the gate
delay for a symmetrical CMOS inverter with
V
Tn
=V
Tp

≡
V
T
,C
o
*
xn
=C
o
*
xp
≡
C
o
*
x
,andK
n
=K
p
,
in which both the n and pchannel devices were minimum
gate length devices, i.e., L
n
=L
p
=L
min
. The pchannel
device was made twice as wide as the nchannel device to
get the desired K equality, because we assumed µ
e
=2µ
h
.
We found that the gate delay was given by:
GD
4!C
L
!V
DD
K
n
(V
DD
!!V
T
)
2
Replacing C
L
and K
n
, to write this in terms of the device
dimensions, we found after a bit of simple algebra:
GD
12!n
µ
e
L
m
2
in
V
DD
(V
DD
!!V
T
)
2
POWER
There is zero static power in CMOS so the only contri
bution is the dynamic power
P
ave
=C
L
V
D
2
D
f
where f is the operating frequency and C
L
is the loading
capacitance.
This load will be the average fanout, n, times
the input capacitance of a similar CMOS gate, plus any
parasitic interconnect capacitance:
C
L
=nC
o
*
x
(L
min
W
n
+L
min
W
p
)+C
parasitic
= 3nC
o
*
x
L
min
W
n
+C
parasitic
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Neglecting C
parasitic
, we can write
P
ave
=3nC
o
*
x
L
min
W
n
V
D
2
D
f
MAXIMUM POWER
The maximum power dissipation will occur when the
gate is operated at its maximum frequency (bit rate), which
is in turn proportional to 1/
GD
. Thus we can say
P
ave max
µ
3nC
o
*
x
L
min
W
n
V
D
2
D
1
GD
=
1
4
W
n
L
min
µ
e
C
o
*
x
V
DD
(V
DD
V
T
)
2
=
1
4
K
n
V
DD
(V
DD
V
T
)
2
The importance of keeping V
DD
small is quite evident from
this expression, but the situation is not black and white
because making V
DD
small makes
GD
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This note was uploaded on 07/20/2009 for the course CSAIL 6.012 taught by Professor Prof.cliftonfonstadjr. during the Fall '03 term at MIT.
 Fall '03
 Prof.CliftonFonstadJr.

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