ps08 - 1 MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department...

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1 MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6.012 ELECTRONIC DEVICES AND CIRCUITS Problem Set No. 8 Issued: October 24, 2003 Due: October 31, 2003 Reading Assignments: Lecture 15 (10/26/03) - Chap. 15 (15.1, 15.2) Lecture 16 (10/28/03) - Chap. 15 (15.2.4) Lecture 17 (10/30/03) - Chap. 11 (11.1, 11.2) Lecture 18 (11/4/03) - Chap. 11 (11.3 to end) Lecture 19 (11/6/03) - Chap. 12 (12.1, 12.2) The second hour exam is scheduled for Wednesday night, November 5, from 7:30 to 9:30 pm in Room 10-250. The exam is closed book and will cover the material through 10/29/03 and Problem Set #8, including BJT operation and large signal modeling; the MOS capacitor; MOSFET operation and large signal modeling; incremental models for diodes, BJTs, and MOSFETs; and MOSFET inverters. There will be no weblab or HSPICE questions on the exam. Problem 1 - (a) Do Problem 15.8 in the course text, doing only case V TN =|V TP | = 0.5 V in Part b of this problem (that is, do not do 0.75 V). Use a = 1. Also, in Part b, consider the statement made that it should be clear to you that it is desirable to reduce the threshold voltage. This might not be so clear. In fact good reasons can be found for making the the threshold large, also. Give some arguments on each side, and particularly in Part c discuss how large and how small V T could safely be made if the process being used gives you an uncertainty of ±0.1 V in V T . (b) Do Problem 15.7 in the course text. Problem 2 - Do Problem 10.1 in the course text using L = 0.25 µm (rather than 1.0 µm as specified in the problem statement). Problem 3 - This problem deals with CMOS inverters fabricated using a process for which the minimum gate length and width are L min and W min , respectively. In order to obtain symmetrical transfer characteristics and minimize the gate delay, the inverters are designed to have V Tn =|V Tp |, t oxn = t oxp , and K n = K p . All the inverters have minimum length gates, i.e., L n =L p =L min , and the width of the p-channel devices is twice that of the n-channel devices, i.e., W p =2W n , because the hole and electron mobilities in the channel differ by a factor of two, i.e., µ e =2 µ p . The smallest inverters have W n =W min and W p = 2 W min , and we will call the corresponding K value K min .
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ps08 - 1 MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department...

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