hw1 - Fall 2005 6.012 Microelectronic Devices and Circuits...

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Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo Homework #1 - September 9, 2005 Due: September 16, 2005 at recitation 2 PM latest) (late homework will not be accepted) Please write your recitation session time on your problem set solution. 1. [60 points] A Dynamic Random Access Memory (DRAM) chip is composed of many cells that hold individual bits of information. For example, a 4 MB DRAM has about 4 × 10 6 cells where information can be held. At the heart of one of these cells is a capacitor that stores electrical charge. If the capacitor is charged, then we say that a ”1” is stored. If the capacitor is discharged, then a ”0” is stored. The smaller the capacitor, the denser the memory chip can be made. Achieving denser DRAM chips has been for the better part of the last 30 years a powerful technology driver for microelectronics, bringing along with it staggering progress in microprocessors and many other microelectronic products. For a long time, the minimum feature size , or minimum dimension that can be reliably fab- ricated on a Si wafer, has been the bottleneck to high-density DRAM development. This is because the storage capacitor area is directly related to the minimum feature dimensions. As technology progressed and the minimum features size decreased, DRAM density increased. In the mid 90’s, however, the situation changed dramatically. Rather than feature size, dielectric breakdown became a limiting phenomenom. This problem explores these issues. This problem is designed to accomplish two goals: 1. to make you understand a few key issues in DRAM development: evolution, critical dimensions, limiting factors; 2. to make you review basic capacitor facts: charge, capacitance, field. To a reasonable good approximation, a DRAM capacitor is basically a parallel plate capac- itor where the insulator is made out of SiO 2 and the plates are made out of heavily-doped polycristalline Si. This, for all purposes, can be thought of as a metal, as you will come to understand soon in 6.012. 1. [5 points] Consider for a moment a 10 μm 2 area capacitor with a 30 nm thick SiO 2 dielectric. Compute the capacitance. The dielectric constant of SiO 2 is 3.9. (
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SiO 2 dielectric SiO 2 field oxide poly-Si plate metal contact Si substrate poly-Si plate 2. [15 points] With 4 V applied across this capacitor, quantitatively sketch the charge distribution, electric field, and electrostatic potential across the capacitor from plate to plate. 3. [25 points] Let’s now look at the evolution of DRAMs. The following table contains the DRAM generation (4M, for example, means a DRAM with about four million bits), the year in which volume production started, and the minimum feature size used in that generation: DRAM year volume minimum feature generation production size ( μm ) 1K 1972 4.6 4K 1974 3.2 16K 1977 2.4 64K 1980 1.8 256K 1983 1.5 1M 1986 1 4M 1989 0.8 16M 1992 0.5 64M 1995 0.35 256M 1998 0.25 1G 2001 0.18
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  • Fall '05
  • Prof.JesúsdelAlamo
  • Permittivity, Parallel Plate Capacitor, SiO2, Dielectric, minimum feature size

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