# lec13 - 6.012 Microelectronic Devices and Circuits Fall...

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits October 25, 2005 Contents : 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS inverter with current-source pull-up 3. Complementary MOS (CMOS) Inverter Reading assignment: Howe and Sodini, Ch. 5, § 5.3

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-2 Key questions What are the key design trade-oﬀs of the NMOS in- verter with resistor pull-up? How can one improve upon these trade-oﬀs? What is special about a CMOS inverter?
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-3 1. NMOS inverter with resistor pull-up (cont.) V IN V OUT V + = V DD I R I D C L R V OUT =V DS V OUT =V IN V IN =V GS 0 0 V DD V T V OH =V MAX =V DD V OL =V MIN V M V IL V IH V M slope= A v (V M ) ± Noise margins: NM L = V IL - V OL = V M - V MAX - V M | A v ( V M ) | - V MIN NM H = V OH - V IH = V MAX - V M (1+ 1 | A v ( V M ) | )+ V MIN | A v ( V M ) | Need to compute | A v ( V M ) | .

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-4 Small-signal equivalent circuit model at V M (transistor in saturation): G S D + - v in + - v gs + - v out g m v gs r o R + - v in + - v out g m v in r o //R v out = - g m v in ( r o //R ) Then: A v = v out v in = - g m ( r o //R ) ±- g m R Then: | A v ( V M ) | = g m ( V M ) R From here, get NM L and NM H using above formulae.
Lecture 13-5 ± Dynamics C L pull-down limited by current through transistor [will study in detail with CMOS] C L pull-up limited by resistor ( t PLH RC L ) pull-up slowest

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## This note was uploaded on 07/20/2009 for the course ELECTRICAL 6.012 taught by Professor Prof.jesúsdelalamo during the Fall '05 term at MIT.

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lec13 - 6.012 Microelectronic Devices and Circuits Fall...

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