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lec14 - 6.012 Microelectronic Devices and Circuits Fall...

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6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 14­1 Lecture 14 ­ Digital Circuits (III) CMOS October 27, 2005 Contents : 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter: noise margins 3. CMOS inverter: propagation delay 4. CMOS inverter: dynamic power Reading assignment: Howe and Sodini, Ch. 5, § 5.4 Announcements: Cadence tutorial by Kerwin Johnson in place of reg­ ular recitations on Friday 10/28
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6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 14­2 Key questions How does CMOS work? What is special about CMOS as a logic technology? What are the key design parameters of a CMOS in­ verter? How can one estimate the propagation delay of a CMOS inverter? Does CMOS burn any power?
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6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 14­3 1. Complementary MOS (CMOS) Inverter Circuit schematic: V DD V IN V OUT C L Basic operation: V IN = 0 V OU T = V DD V GSn = 0 < V NMOS OFF Tn V SGp = V DD > V Tp PMOS ON V IN = V DD V OU T = 0 V GSn = V DD > V Tn NMOS ON V SGp = 0 < V Tp PMOS OFF ±
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6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 14­4 Output characteristics of both transistors: I Dn V SGp V SGp =-V Tp 0 0 V DSn 0 V SDp -I Dp 0 V GSn V GSn =V Tn Note: V IN = V GSn = V DD V SGp V SGp = V DD V IN V OU T = V DSn = V DD V SDp V SDp = V DD V OU T I Dn = I Dp Combine into single diagram of I D vs. V OU T with V IN as parameter.
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6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 14­5 V DD I D V IN V OUT V DD -V IN V IN C L 0 0 V OUT no current while idling in any logic state . Transfer function: NMOS cutoff� PMOS triode V OUT V IN 0 0 V DD V Tn V DD +V Tp V DD NMOS saturation� PMOS triode NMOS saturation� PMOS saturation NMOS triode� PMOS saturation NMOS triode� PMOS cutoff ”rail­to­rail” logic: logic levels are 0 and V DD high A v around logic threshold good noise margins |
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6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 14­6 Transfer characteristics of CMOS inverter in WebLab:
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6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 14­7 2. CMOS inverter: noise margins V OUT V DD V M 0 A v ( V M ) NM L 0 V IL V M V IH V DD V IN NM H Calculate V M Calculate A v ( V M ) Calculate NM L and NM H Calculate V M ( V M = V IN = V OUT ) At V M both transistors saturated: 1 W n I Dn = µ
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