cpld - Massachusetts Institute of Technology Department of...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory CPLD Module Created 09/20/99 by D. Seth Revised 01/31/01 by D. Troxel The CPLD module comprises of four interconnected Cypress 374I CPLD's that can be accessed via the kit's NuBus interface and 50-pin connectors. The state of the I/O lines of the NuBus interconnects are displayed on the HEX LED's while the I/O lines of the 50 pin connector extend directly to the inputs of the Logic Analyzer. The diagram below shows the architecture of the module and its interface to the kit.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Figure 1: System Diagram The major components of the module can be categorized into the NuBus Interface, the 50-pin connector Interface, the Interconnect Bus, the Serial Interface, the Programming Interface and the Clocking Scheme. NuBus Interface 31 I/O pins of each CPLD are interconnected and extended to the NuBus connector. For example, IO-0 of all 4 CPLD's are tied together to NuBus Address A0. Table 1 elaborates these interconnections.
Background image of page 2
Table 1: NuBus Interface 50-Pin Connector Interface 25 I/O pins are interconnected among the 4 CPLD's and the 50-pin connector. The signals of the 50-pin connector interface directly to the logic analyzer via the connector on the kit. Table 2 provides details of these interconnections. Logic Blocks are partitions internal to the CPLD chip. This information, at times, can be useful during device fitting. Table 2: 50-pin Connector Interface Note: If you use K1, then IO-53 must not be used. Similarly, if you use K2, then IO-11 must not be used. Serial Interface The CPLD Module supports an RS-232 interface via the DB-9 Male connector. The received serial data from Pin 2 of the DB-9 is brought to logic levels via
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
inversion from a MAX 233 and is made available on Pin 12 of CPLD 1. The data to be transmitted is presented at Pin 73 of CPLD 1, which appears on Pin 3 of the DB-9 after being inverted by the MAX 233. Please see /mit/6.111/vhdl/serial/ for VHDL code that emulates a receiver and a transmitter. Clock Interface Figure 2 below presents the clocking scheme used by the module. Figure 2: Clocking Scheme The following are some clocking strategies that can be utilized: 1. C1 sources its clock from the oscillator by enabling jumper J8, while C [2,3 or 4] can buffer this signal (IO-9) to any connection on the NuBus, e.g. A30. A short circuit can then be created between this interconnection, i.e. A30 and A31 by installing a jumper wire. 2. C [2,3 or 4] buffer A31 to IO-9 thereby clocking C1. In this scenario, jumper J8 is removed and an external clock is supplied to A31. 3. Jumper J8's strategic location makes it possible to insert a wire within the jumper and plug the other end into NuBus A31. If this is done, a termination resistor (discussed ahead) may be required between A31 and GND located on the NUBus connector. 4.
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 17

cpld - Massachusetts Institute of Technology Department of...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online