l3 - 6.111 Lecture # 3 X 1 Z X 2 Simplified Schematic of...

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Unformatted text preview: 6.111 Lecture # 3 X 1 Z X 2 Simplified Schematic of 74LS00 (there are 4 of these in an '00) Note multiple emitter inputs NAND gate is the basic building block Totem pole output Current Convention 74LS00 Current (mA) Output capability LOW I OL 8 mA Output Capability HIGH I OH -400 A Input Required LOW I IL -0.4 mA Input Required HIGH IIH 20 A These are typical numbers but read data sheet if in doubt: There are many exceptions TTL Voltage Ranges These are important! Valid input and output values are in the ranges shown. Note that the TRUE switching threshold will be different for different parts or instruments -- in doubt, best us a 'scope Note that either 'state' (X=0, Y=1 or X=1, Y=0) is valid Try this in the lab... 'State' implies memory -- here is how we save information You can build one of these from NAND gates, but there is a packaged, MSI version. Question: what happens if you build one from NOR gates? 'Latch' is an important notion: its input is controlled by a 'gate' When the 'gate' goes from high to low, the state of the device holds Question: what happens if the input and gate change state at nearly the same time? the same time?...
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l3 - 6.111 Lecture # 3 X 1 Z X 2 Simplified Schematic of...

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