l5 - 6.111 Lecture 5 VHDL Very High speed integrated...

Info icon This preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
6.111 Lecture # 5 VHDL: Very High speed integrated circuit Description Language: All VHDL files have two sections: architecture and entity -- Massachusetts (Obsolete) Stoplight Example library ieee; use ieee.std_logic_1164.all; entity check is port(r, y, g: in std_logic; ok: out std_logic); end check; architecture logical of check is signal t1, t2, t3: std_logic; begin t1 <= r and (not g); t2 <= y and (not g); t3 <= (not r) and (not y) and g; ok <= t1 or t2 or t3; Entity section describes input and output Architecture section describes what to do with those signals end logical;
Image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
library clause describes the basic library to make reference to use clause establishes definitions of many important items for most situations, use these 'as is' library ieee; use ieee.std_logic_1164.all; Other libraries will be used and you will have the opportunity to make libraries of your own.
Image of page 2
The entity declaration can be quite complex and has a lot of information I/O signals are referrred to as PORT s. These signals have Mode and Type The Mode of a signal can be in , out , buffer or inout in and out are straightforward buffer is like out , but is available within the architecture inout is a tri-state (bidirectional) Note how vectors (multi-bit) signals are handled.
Image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
We can avoid using Mode BUFFER Note the additional declaration of signal inside the architecture section. Note the names in the architecture section need not be unique and are there for readability
Image of page 4
Type of signals are defined in LIBRARY ieee; use ieee.std_logic_1164.all; (VHDL is defined by IEEE Standard 1164) std_logic types can take values:
Image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern