l8 - 6.111 Lecture 8 Topics for Today(as time permits 1...

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6.111 Lecture # 8 Topics for Today: (as time permits) 1. Memories 2. Assembling 'packages' for designs 3. Discussion of design procedure 4. Development of a design example using a finite state machine Preview: No class Monday (Student Holiday) Wednesday: quiz rev iew and discussion of Phase II Friday: Quiz 1
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Memories are usually organized as 2- dimensional arrays of cells Address is split into two parts e.g. 4k = 4096 addresses = 2 14 might have 7 bits of address for each of row and column
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Conceptual Memory Cell: This is what goes at each intersection of the row and column lines (i.e. there are a lot of these!) Note how this is like a 'D-Latch' The lines D and D* are from the row decoder and control. D = D* = '1' => 'Read': cell contents go onto sense lines D = D* = '0' => This row is not addressed. Output is high (collectors open and some other row drives sense lines) D = /D* and G = '1': 'Write': D is latched onto cell when G goes low Output of this cell is 'open collector' and so "pulls down" the sense lines that go to the column decoding MUX
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Control Lines: Often Active Low OE is 'Output Enable' WE is 'Write Enable' CS is 'Chip Select' If: /WE is LOW, /CS is LOW, /OE is HIGH, Data pins are input Input data is written to chip If /WE is HIGH /CS is LOW /OE is LOW Data pins are output Date is read from memory
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Some have simpler control structure The /OE line is in many cases redundant (but having the extra line to use can be convenient) In these parts, Read => /CS = LOW and /WE = HIGH Write => /CS = LOW and /WE = LOW
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Read Cycle Timing Address takes a little while to propagate into the right places It takes a bit less time for the part to 'grab' the output pins (invalid data may be on them initially) And note it takes a little while after /CS goes high for the part to let go of the output pins And if Address goes invalid before /CS goes high, there may be invalid data on the output pins
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Write cycle timing is a little more complex ==> It is most important that Address and Data must BOTH be valid during the write pulse <== ==> It is also important that Address must be fixed and valid during the Whole of the write pulse <== ==> Data must be valid for a period at the end of the write pulse <== Tristated or unstable address lines can wind up writing garbage to a large number of memory locations!
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Here is a general purpose suggestion for handling memory in a FSM controlled system. You can do it more simply in Lab 2 Driving /CS with /CLK ensures 'clean' write pulses and reduces the possibility of bus contention. Both WRITE and READ operations are enabled only on the second half of the clock cycle (before the positive going edge)
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This timing diagram illustrates how the scheme on the previous slide might work. It assumes Addr changes after the positive going clock edge and so is stable when the clock is low.
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